High Performance Loop Filter Design for Continuous-time Sigma-delta ADC

Continuous-time (CT) sigma-delta (ΣΔ) analog-to-digital converters (ADCs) are widely used in wireless transceiver. Loop filter becomes a critical component in the implementation of high resolution large bandwidth CT ΣΔ ADC because it determines loop stability and defines quantization noise-shaping behavior of the ΣΔ modulator. In this thesis, an extremely low power loop filter for 11-bit dynamic range 15MHz CT ΣΔ ADC is described. On the system level, a new local feedback structure which consists of a CT differentiator in cascade with an integrator is proposed to solve the problem of excess loop delay and eliminate the use of a power-hungry summing amplifier. Proposed continuous-time differentiator is demonstrated to make the whole ΣΔ loop more robust to delay variation and easier designed than previously published discrete-time differentiator. On the circuit level, two-stage operational amplifiers with new class-AB output stages are used to implement low-power active RC integrators. The proposed class-AB output stage is proven to be more linear than conventional one. The whole ΣΔ ADC circuit was designed, simulated and implemented in IBM 130nm CMOS technology. The designed loop filter including CT differentiator draws less than 3mA from 1.2V supply voltage

Contribución al modelado y diseño de moduladores sigma-delta en tiempo continuo de baja relación de sobremuestreo y bajo consumo de potencia

Continuous-Time Sigma-Delta modulators are often employed as analog-to-digital converters. These modulators are an attractive approach to implement high-speed converters in VLSI systems because they have low sensitivity to circuit imperfections compared to other solutions. This work is a contribution to the analysis, modelling and design of high-speed Continuous-Time Sigma-Delta modulators. The resolution and the stability of these modulators are limited by two main factors, excess-loop delay and sampling uncertainty. Both factors, among others, have been carefully analysed and modelled. A new design methodology is also proposed. It can be used to get an optimum high-speed Continuous-Time Sigma-Delta modulator in terms of dynamic range, stability and sensitivity to sampling uncertainty. Based on the proposed design methodology, a software tool that covers the main steps has been developed. The methodology has been proved by using the tool in designing a 30 Megabits-per-second Continuous-Time Sigma-Delta modulator with 11-bits of dynamic range. The modulator has been integrated in a 0.13-µm CMOS technology and it has a measured peak SNR of 62.5dB

Low Power Continuous-time Bandpass Delta-Sigma Modulators.

Low power techniques for continuous-time bandpass delta-sigma modulators (CTBPDSMs) are introduced. First, a 800MS/s low power 4th-order CTBPDSM with 24MHz bandwidth at 200MHz IF is presented. A novel power-efficient resonator with a single amplifier is used in the loopfilter. A single op-amp resonator makes use of positive feedback to increase the quality factor. Also, a new 4th-order architecture is introduced for system simplicity and low power. Low power consumption and a simple modulator structure are achieved by reducing the number of feedback DACs. This modulator achieves 58dB SNDR, and the total power consumption is 12mW. Second, a 6th-order CTBPDSM with duty cycle controlled DACs is presented. This prototype introduces new architecture for low power consumption and other important features. Duty cycle control enables the use of a single DAC per resonator without degrading the signal transfer function (STF), and helps to lower power consumption, low area, and thermal noise. This ADC provides input signal filtering, and increases the dynamic range by reducing the peaking in the STF. Furthermore, the center frequency is tunable so that the CTBPDSM is more useful in the receiver. The prototype second modulator achieves 69dB SNDR, and consumes 35mW, demonstrating the best FoM of 320fJ/conv.-step for CTBPDSMs using active resonators. The techniques introduced in this research help CTBPDSMs have good power efficiency compared with the other kinds of ADCs, and make the implement of a software-defined radio architecture easier which is appropriate for the future multiple standard radio receivers without a power penalty.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98001/1/hichae_1.pd

Comparison of Simulation Methods of Single and Multi-Bit Continuous Time Sigma Delta Modulators

Continuous time Sigma Delta Modulators (CT ΣΔMs) are a type of analog to digital converter (ADC) that are used in mixed signal systems to convert analog signals into digital signals. ADCs typically require antialiasing filter; however antialiasing filters are inherent in CT ΣΔMs, and therefore they require less circuitry and less power than other ADC architectures that require separate antialiasing filters. As a result, CT ΣΔM ADC architectures are preferred in many mixed signal electronic applications. Because of the mixed signal nature of CT ΣΔMs, they can be difficult to simulate. In this thesis, various methods for simulating single-bit and multi-bit CT ΣΔMs are developed and these simulations include the bilinear transform or trapezoidal integration, impulse invariance transform, midpoint integration, Simpson’s rule, delta transform or Euler’s forward integration rule and Simulink modeling. These methods are compared with respect to speed which is given by the total simulation time, accuracy which is given by the signal to noise ratio (SNR) value and the simplicity of the simulation method. The CT ΣΔMs have been extended from first order up to fifth order with one, two and three bit quantizers. Also, the frequency domain analysis is done for all the orders of CT ΣΔMs. The results show that the numerical integration methods are more accurate and faster than Simulink. However, CT ΣΔM simulations using Simulink are simpler because of the availability of the required blocks in Simulink. The overall comparison shows that the numerical integration methods can perform better than Simulink models. The frequency domain analysis proves the correctness of the use of numerical integration methods for CT ΣΔM simulations

Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters

There is a significant need in recent mobile communication and wireless broadband systems for high-performance analog-to-digital converters (ADCs) that have wide bandwidth (BW>5-MHz) and high data rate (>100-Mbps). A delta-sigma ADC is recognized as a power-efficient ADC architecture when high resolution (>12-b) is required. This is due to several advantages of the delta-sigma ADC including relaxed anti-aliasing filter requirements, high signal-to-noise and distortion ratio (SNDR) and most importantly, reduced sensitivity to analog imperfections. In this thesis, several structures and design techniques are developed for the implementation of continuoustime (CT) and discrete-time (DT) delta-sigma ADCs. These techniques save the total power consumption, reduce the design complexity, and decrease the chip die area of delta-sigma modulators. First a 4th-order single stage CT delta-sigma ADC with a novel single-amplifier-biquad (SAB) based loop filter is presented. By utilizing the SAB networks in the loop filter of an Nth-order CT delta-sigma modulator, it requires only half the number of active amplifiers and feed-forward branches used in the conventional modulator architecture, thus decreasing the power consumption and area by reducing the number of amplifiers. The proposed scheme also enables the modulator to use a switch-capacitor (SC) adder due to the reduced number of feedforward branches to its summing block. As a sequence, it consumes less power compared to a conventional CT adder. With a 130-nm CMOS technology, the fabricated prototype IC achieves a dynamic range of 80 dB with 10 MHz signal bandwidth and analog power dissipation lower than 12 mW. Presented as the second scheme to save power consumption and chip die area in ΔΣ modulators is a new stage-sharing technique in a discrete-time 2-2 MASH ΔΣ ADC. The proposed technique shares all the active blocks of the modulator second stage with its first stage during the two non-overlapping clock phases. Measurement results show that the modulator designed in a 0.13-um CMOS technology achieves 76 dB SNDR over a 10 MHz conversion bandwidth dissipating less than 9 mW analog power

Area- and Energy- Efficient Modular Circuit Architecture for 1,024-Channel Parallel Neural Recording Microsystem.

This research focuses to develop system architectures and associated electronic circuits for a next generation neuroscience research tool, a massive-parallel neural recording system capable of recording 1,024 channels simultaneously. Three interdependent prototypes have been developed to address major challenges in realization of the massive-parallel neural recording microsystems: minimization of energy and area consumption while preserving high quality in recordings. First, a modular 128-channel Δ-ΔΣ AFE using the spectrum shaping has been designed and fabricated to propose an area-and energy efficient solution for neural recording AFEs. The AFE achieved 4.84 fJ/C−s·mm2 figure of merit that is the smallest the area-energy product among the state-of-the-art multichannel neural recording systems. It also features power and area consumption of 3.05 µW and 0.05 mm2 per channel, respectively while exhibiting 63.3 dB signal-to-noise ratio with 3.02 µVrms input referred noise. Second, an on-chip mixed signal neural signal compressor was built to reduce the energy consumption in handling and transmission of the recorded data since this occupies a large portion of the total energy consumption as the number of parallel recording increases. The compressor reduces the data rates of two distinct groups of neural signals that are essential for neuroscience research: LFP and AP without loss of informative signals. As a result, the power consumptions for the data handling and transmissions of the LFP and AP were reduced to about 1/5.35 and 1/10.54 of the uncompressed cases, respectively. In the total data handling and transmission, the measured power consumption per channel is 11.98 µW that is about 1/9 of 107.5 µW without the compression. Third, a compact on-chip dc-to-dc converter with constant 1 MHz switching frequency has been developed to provide reliable power supplies and enhance energy delivery efficiency to the massive-parallel neural recording systems. The dc-to-dc converter has only predictable tones at the output and it exhibits > 80% power conversion efficiency at ultra-light loads, < 100 µW that is relevant power most of the multi-channel neural recording systems consume. The dc-to-dc converter occupies 0.375 mm2 of area which is less than 1/20 of the area the first prototype consumes (8.64 mm2).PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/133244/1/sungyun_1.pd

Low-voltage low-power continuous-time delta-sigma modulator designs

Ph.DDOCTOR OF PHILOSOPH