2,385 research outputs found
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Constant-time cost evaluation for behavioral partitioning
Given a system behavioral specification, partitioning can be used to distribute among chips the processes, procedures, and storage elements that comprise the specification. We introduce a technique for constant-time recomputation of pin, area, and execution-time estimates for a behavioral partitioning move. The technique permits fast, accurate estimations of a large number of partitionings, thus enabling better results than approaches which attain tractable computation time by using gross estimates or less thorough partitioning algorithms. The key to our technique is the isolation and extraction before partitioning of the basic design attributes needed for estimation, and the updating of this information in constant-time for each move. The estimation models are almost as detailed as those presented in previous estimation approaches not intended for constant-time update. The results we provide indicate the speed and practicality of our estimation approach in conjunction with sophisticated partitioning algorithms
Novel fault tolerant Multi-Bit Upset (MBU) Error-Detection and Correction (EDAC) architecture
Desde el punto de vista de seguridad, la certificación aeronáutica de
aplicaciones críticas de vuelo requiere diferentes técnicas que son usadas
para prevenir fallos en los equipos electrónicos. Los fallos de tipo hardware
debido a la radiación solar que existe a las alturas standard de vuelo, como
SEU (Single Event Upset) y MCU (Multiple Bit Upset), provocan un cambio
de estado de los bits que soportan la información almacenada en memoria.
Estos fallos se producen, por ejemplo, en la memoria de configuración de
una FPGA, que es donde se definen todas las funcionalidades. Las técnicas
de protección requieren normalmente de redundancias que incrementan el
coste, número de componentes, tamaño de la memoria y peso.
En la fase de desarrollo de aplicaciones críticas de vuelo, generalmente
se utilizan una serie de estándares o recomendaciones de diseño como
ABD100, RTCA DO-160, IEC62395, etc, y diferentes técnicas de protección
para evitar fallos del tipo SEU o MCU. Estas técnicas están basadas en
procesos tecnológicos específicos como memorias robustas, codificaciones
para detección y corrección de errores (EDAC), redundancias software,
redundancia modular triple (TMR) o soluciones a nivel sistema.
Esta tesis está enfocada a minimizar e incluso suprimir los efectos de los
SEUs y MCUs que particularmente ocurren en la electrónica de avión como
consecuencia de la exposición a radiación de partículas no cargadas (como
son los neutrones) que se encuentra potenciada a las típicas alturas de
vuelo. La criticidad en vuelo que tienen determinados sistemas obligan a que
dichos sistemas sean tolerantes a fallos, es decir, que garanticen un
correcto funcionamiento aún cuando se produzca un fallo en ellos. Es por
ello que soluciones como las presentadas en esta tesis tienen interés en el
sector industrial.
La Tesis incluye una descripción inicial de la física de la radiación
incidente sobre aeronaves, y el análisis de sus efectos en los componentes
electrónicos aeronaúticos basados en semiconductor, que desembocan en
la generación de SEUs y MCUs. Este análisis permite dimensionar
adecuadamente y optimizar los procedimientos de corrección que se
propongan posteriormente.
La Tesis propone un sistema de corrección de fallos SEUs y MCUs que
permita cumplir la condición de Sistema Tolerante a Fallos, a la vez que
minimiza los niveles de redundancia y de complejidad de los códigos de
corrección. El nivel de redundancia es minimizado con la introducción del
concepto propuesto HSB (Hardwired Seed Bits), en la que se reduce la
información esencial a unos pocos bits semilla, neutros frente a radiación.
Los códigos de corrección requeridos se reducen a la corrección de un único
error, gracias al uso del concepto de Distancia Virtual entre Bits, a partir del
cual será posible corregir múltiples errores simultáneos (MCUs) a partir de
códigos simples de corrección.
Un ejemplo de aplicación de la Tesis es la implementación de una
Protección Tolerante a Fallos sobre la memoria SRAM de una FPGA. Esto
significa que queda protegida no sólo la información contenida en la
memoria sino que también queda auto-protegida la función de protección
misma almacenada en la propia SRAM. De esta forma, el sistema es capaz
de auto-regenerarse ante un SEU o incluso un MCU, independientemente
de la zona de la SRAM sobre la que impacte la radiación. Adicionalmente,
esto se consigue con códigos simples tales como corrección por bit de
paridad y Hamming, minimizando la dedicación de recursos de computación
hacia tareas de supervisión del sistema.For airborne safety critical applications certification, different techniques
are implemented to prevent failures in electronic equipments. The HW
failures at flying heights of aircrafts related to solar radiation such as SEU
(Single-Event-Upset) and MCU (Multiple Bit Upset), causes bits alterations
that corrupt the information at memories. These HW failures cause errors, for
example, in the Configuration-Code of an FPGA that defines the
functionalities. The protection techniques require classically redundant
functionalities that increases the cost, components, memory space and
weight.
During the development phase for airborne safety critical applications,
different aerospace standards are generally recommended as ABD100,
RTCA-DO160, IEC62395, etc, and different techniques are classically used
to avoid failures such as SEU or MCU. These techniques are based on
specific technology processes, Hardened memories, error detection and
correction codes (EDAC), SW redundancy, Triple Modular Redundancy
(TMR) or System level solutions.
This Thesis is focussed to minimize, and even to remove, the effects of
SEUs and MCUs, that particularly occurs in the airborne electronics as a
consequence of its exposition to solar radiation of non-charged particles (for
example the neutrons). These non-charged particles are even powered at
flying altitudes due to aircraft volume. The safety categorization of different
equipments/functionalities requires a design based on fault-tolerant approach
that means, the system will continue its normal operation even if a failure
occurs. The solution proposed in this Thesis is relevant for the industrial
sector because of its Fault-tolerant capability.
Thesis includes an initial description for the physics of the solar radiation
that affects into aircrafts, and also the analyses of their effects into the
airborne electronics based on semiconductor components that create the
SEUs and MCUs. This detailed analysis allows the correct sizing and also
the optimization of the procedures used to correct the errors.
This Thesis proposes a system that corrects the SEUs and MCUs
allowing the fulfilment of the Fault-Tolerant requirement, reducing the
redundancy resources and also the complexity of the correction codes. The
redundancy resources are minimized thanks to the introduction of the
concept of HSB (Hardwired Seed Bits), in which the essential information is
reduced to a few seed bits, neutral to radiation. The correction codes
required are reduced to the correction of one error thanks to the use of the
concept of interleaving distance between adjacent bits, this allows the
simultaneous multiple error correction with simple single error correcting
codes.
An example of the application of this Thesis is the implementation of the
Fault-tolerant architecture of an SRAM-based FPGA. That means that the
information saved in the memory is protected but also the correction
functionality is auto protected as well, also saved into SRAM memory. In this
way, the system is able to self-regenerate the information lost in case of
SEUs or MCUs. This is independent of the SRAM area affected by the
radiation. Furthermore, this performance is achieved by means simple error
correcting codes, as parity bits or Hamming, that minimize the use of
computational resources to this supervision tasks for system.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Luis Alfonso Entrena Arrontes.- Secretario: Pedro Reviriego Vasallo.- Vocal: Mª Luisa López Vallej
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Survey of unified approaches to integrated-service networks
The increasing demand for communication services, coupled with recent technological advances in communication media and switching techniques, has resulted in a proliferation of new and expanded services. Currently, networks are needed which can transmit voice, data, and video services in an application-independent fashion. Unified approaches employ a single switching technique across the entire network bandwidth, thus, allowing services to be switched in an application-independent manner. This paper presents a taxonomy of integrated-service networks including a look at N-ISDN, while focusing on unified approaches to integrated-service networks.The two most promising unified approaches are burst and fast packet switching. Burst switching is a circuit switching-based approach which allocates channel bandwidth to a connection only during the transmission of "bursts" of information. Fast packet switching is a packet switching-based approach which can be characterized by very high transmission rates on network links and simple, hardwired protocols which match the rapid channel speed of the network. Both approaches are being proposed as possible implementations for integrated-service networks. We survey these two approaches, and also examine the key performance issues found in fast packet switching. We then present the results of a simulation study of a fast packet switching network
Initial flight qualification and operational maintenance of X-29A flight software
A discussion is presented of some significant aspects of the initial flight qualification and operational maintenance of the flight control system softward for the X-29A technology demonstrator. Flight qualification and maintenance of complex, embedded flight control system software poses unique problems. The X-29A technology demonstrator aircraft has a digital flight control system which incorporates functions generally considered too complex for analog systems. Organizational responsibilities, software assurance issues, tools, and facilities are discussed
Low-overhead fault-tolerant logic for field-programmable gate arrays
While allowing for the fabrication of increasingly complex and efficient circuitry, transistor shrinkage and count-per-device expansion have major downsides: chiefly increased variation, degradation and fault susceptibility. For this reason, design-time consideration of faults will have to be given to increasing numbers of electronic systems in the future to ensure yields, reliabilities and lifetimes remain acceptably high. Many mathematical operators commonly accelerated in hardware are suited to modification resulting in datapath error detection and correction capabilities with far lower area, performance and/or power consumption overheads than those incurred through the utilisation of more established, general-purpose fault tolerance methods such as modular redundancy. Field-programmable gate arrays are uniquely placed to allow further area savings to be made thanks to their dynamic reconfigurability.
The majority of the technical work presented within this thesis is based upon a benchmark hardware accelerator---a matrix multiplier---that underwent several evolutions in order to detect and correct faults manifesting along its datapath at runtime. In the first instance, fault detectability in excess of 99% was achieved in return for 7.87% additional area and 45.5% extra latency. In the second, the ability to correct errors caused by those faults was added at the cost of 4.20% more area, while 50.7% of this---and 46.2% of the previously incurred latency overhead---was removed through the introduction of partial reconfiguration in the third. The fourth demonstrates further reductions in both area and performance overheads---of 16.7% and 8.27%, respectively---through systematic data width reduction by allowing errors of less than ±0.5% of the maximum output value to propagate.Open Acces
Adaptive data synchronization algorithm for IoT-oriented low-power wide-area networks
The Internet of Things (IoT) is by now very close to be realized, leading the world towards a new technological era where people’s lives and habits will be definitively revolutionized. Furthermore, the incoming 5G technology promises significant enhancements concerning the Quality of Service (QoS) in mobile communications. Having billions of devices simultaneously connected has opened new challenges about network management and data exchange rules that need to be tailored to the characteristics of the considered scenario. A large part of the IoT market is pointing to Low-Power Wide-Area Networks (LPWANs) representing the infrastructure for several applications having energy saving as a mandatory goal besides other aspects of QoS. In this context, we propose a low-power IoT-oriented file synchronization protocol that, by dynamically optimizing the amount of data to be transferred, limits the device level of interaction within the network, therefore extending the battery life. This protocol can be adopted with different Layer 2 technologies and provides energy savings at the IoT device level that can be exploited by different applications
Implementation of an integrated quality assurance program for CT-TPS process
Systematic constancy and accuracy of a treatment planning system (TPS) are crucial for the entire radiation treatment planning process (TPP). The Quality Assurance (QA) of individual components does not necessarily lead to satisfying performance of the whole process due to the possible errors introduced by the data transfer process between components and other fluctuations. However, most of current QA for TPS is confined to the treatment planning computers. In this study, a time efficient and integrated CT-TPS QA procedure is presented, which starts at the beginning of the TPS input --- Computer Tomograhpy (CT). The whole QA procedure is based on the concept of simulating a real patient treatment. Following the CT scan of a head phantom with geometrical objects, a set of reference treatment plans for each accelerator, with all energy beams included, were established. Whenever TPS QA is necessary, the same procedure is repeated and a QA plan is produced. Through the comparison of QA plan with the reference plan, major systematic errors can be found easily and quickly. This method was also applied to VariSeed and PLATO Brachytherapy treatment planning systems. Moreover, if any error is detected in the system, TPS is broken into several parts and individual tests are also set up
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