Performance Enhancement in Active Power Filter (APF) by FPGA Implementation

The generated electrical power in present days is not able to meet its end-user requirement as power demand is gradually increasing and expected to be increasing more in future days. In the power quality management, the parameters/factors like harmonic currents (HC) and reactive power (RP) yields the major issues in the power distribution units causing transformer heating, line losses, and machine vibration. To overcome these issues, several control mechanisms have been presented and implemented in recent past. The control algorithm based on synchronous reference frame (SRF) offers a better response by dividing the HC and RP. But the SRF based control algorithm requires better synchronization among the utility voltage and input current. To achieve this, the existing researches have used digital signal processing (DSP) and microcontroller, but these systems fail to provide better performance as they face issues like limited sampling time, less accuracy, and high computational complexity. Thus, to enhance the performance of active power filter (APF), we present an FPGA based approach. Also, to validate the performance of the proposed approach, we have used Xilinx 14.7 and Modelsim (6.3f) simulator and compared with other previous work. From the results analysis, it is found that the approach has good performance

Fast ICA for Blind Source Separation and its Implementation

Independent Component Analysis (ICA) is a statistical signal processing technique having emerging new practical application areas, such as blind signal separation such as mixed voices or images, analysis of several types of data or feature extraction. Fast independent component analysis (Fast ICA ) is one of the most efficient ICA technique. Fast ICA algorithm separates the independent sources from their mixtures by measuring non-gaussian. Fast ICA is a common method to identify aircrafts and interference from their mixtures such as electroencephalogram (EEG), magnetoencephalography (MEG), and electrocardiogram (ECG). Therefore, it is valuable to implement Fast ICA for real-time signal processing. In this thesis, the Fast ICA algorithm is implemented by hand coding HDL code. In addition, in order to increase the number of precision, the floating point (FP) arithmetic units are also implemented by HDL coding.To verify the algorithm, MATLAB simulations are also performed for both off line signal rocessing and real-time signal processing

Development of Novel Independent Component Analysis Techniques and their Applications

Real world problems very often provide minimum information regarding their causes. This is mainly due to the system complexities and noninvasive techniques employed by scientists and engineers to study such systems. Signal and image processing techniques used for analyzing such systems essentially tend to be blind. Earlier, training signal based techniques were used extensively for such analyses. But many times either these training signals are not practicable to be availed by the analyzer or become burden on the system itself. Hence blind signal/image processing techniques are becoming predominant in modern real time systems. In fact, blind signal processing has become a very important topic of research and development in many areas, especially biomedical engineering, medical imaging, speech enhancement, remote sensing, communication systems, exploration seismology, geophysics, econometrics, data mining, sensor networks etc. Blind Signal Processing has three major areas: Blind Signal Separation and Extraction, Independent Component Analysis (ICA) and Multichannel Blind Deconvolution and Equalization. ICA technique has also been typically applied to the other two areas mentioned above. Hence ICA research with its wide range of applications is quite interesting and has been taken up as the central domain of the present work

Synthesis of FPGA-based accelerators implementing recursive algorithms

Doutoramento em Engenharia InformáticaO desenvolvimento de sistemas computacionais é um processo complexo, com múltiplas etapas, que requer uma análise profunda do problema, levando em consideração as limitações e os requisitos aplicáveis. Tal tarefa envolve a exploração de técnicas alternativas e de algoritmos computacionais para optimizar o sistema e satisfazer os requisitos estabelecidos. Neste contexto, uma das mais importantes etapas é a análise e implementação de algoritmos computacionais. Enormes avanços tecnológicos no âmbito das FPGAs (Field-Programmable Gate Arrays) tornaram possível o desenvolvimento de sistemas de engenharia extremamente complexos. Contudo, o número de transístores disponíveis por chip está a crescer mais rapidamente do que a capacidade que temos para desenvolver sistemas que tirem proveito desse crescimento. Esta limitação já bem conhecida, antes de se revelar com FPGAs, já se verificava com ASICs (Application-Specific Integrated Circuits) e tem vindo a aumentar continuamente. O desenvolvimento de sistemas com base em FPGAs de alta capacidade envolve uma grande variedade de ferramentas, incluindo métodos para a implementação eficiente de algoritmos computacionais. Esta tese pretende proporcionar uma contribuição nesta área, tirando partido da reutilização, do aumento do nível de abstracção e de especificações algorítmicas mais automatizadas e claras. Mais especificamente, é apresentado um estudo que foi levado a cabo no sentido de obter critérios relativos à implementação em hardware de algoritmos recursivos versus iterativos. Depois de serem apresentadas algumas das estratégias para implementar recursividade em hardware mais significativas, descreve-se, em pormenor, um conjunto de algoritmos para resolver problemas de pesquisa combinatória (considerados enquanto exemplos de aplicação). Versões recursivas e iterativas destes algoritmos foram implementados e testados em FPGA. Com base nos resultados obtidos, é feita uma cuidada análise comparativa. Novas ferramentas e técnicas de investigação que foram desenvolvidas no âmbito desta tese são também discutidas e demonstradas.Design of computational systems is a complex multistage process which requires a deep analysis of the problem, taking into account relevant limitations and constraints as well as software/hardware co-design. Such task involves exploring competitive techniques and computational algorithms, enabling the system to be optimized while satisfying given requirements. In this context, one of the most important stages is analysis and implementation of computational algorithms. Tremendous progress in the scope of FPGA (Field-Programmable Gate Array) technology has made it possible to design very complicated engineering systems. However, the number of available transistors grows faster than the ability to meaningfully design with them. This situation is a well known design productivity gap, which was inherited by FPGA from ASIC (Application-Specific Integrated Circuit) and which is increasing continuously. Developing engineering systems on the basis of high capacity FPGAs involves a wide variety of design tools, including methods for efficient implementation of computational algorithms. The thesis is intended to provide a contribution in this area by aiming at reuse, high level abstraction, automation, and clearness of algorithmic specifications. More specifically, it presents research studies which have been carried out in order to obtain criteria regarding implementation of recursive vs. iterative algorithms in hardware. After describing some of the most relevant strategies for implementing recursion in hardware, a selection of algorithms for solving combinatorial search problems (considered as application examples) are also described in detail. Iterative and recursive versions of these algorithms have been implemented and tested in FPGA. Taking into consideration the results obtained, a careful comparative analysis is given. New research-oriented tools and techniques for hardware design which have been developed in the scope of this thesis are also discussed and demonstrated