A three-stage ATM switch with cell-level path allocation

A method is described for performing routing in three-stage asynchronous transfer mode (ATM) switches which feature multiple channels between the switch modules in adjacent stages. The method is suited to hardware implementation using parallelism to achieve a very short execution time. This allows cell-level routing to be performed, whereby routes are updated in each time slot. The algorithm allows a contention-free routing to be performed, so that buffering is not required in the intermediate stage. An algorithm with this property, which preserves the cell sequence, is referred to as a path allocation algorithm. A detailed description of the necessary hardware is presented. This hardware uses a novel circuit to count the number of cells requesting each output module, it allocates a path through the intermediate stage of the switch to each cell, and it generates a routing tag for each cell, indicating the path assigned to it. The method of routing tag assignment described employs a nonblocking copy network. The use of highly parallel hardware reduces the clock rate required of the circuitry, for a given-switch size. The performance of ATM switches using this path allocation algorithm has been evaluated by simulation, and is described

Upper Bound Analysis and Routing in Optical Benes Networks

Multistage Interconnection Networks (MIN) are popular in switching and communication applications. It has been used in telecommunication and parallel computing systems for many years. The new challenge facing optical MIN is crosstalk, which is caused by coupling two signals within a switching element. Crosstalk is not too big an issue in the Electrical Domain, but due to the stringent Bit Error Rate (BER) constraint, it is a big major concern in the Optical Domain. In this research dissertation, we will study the blocking probability in the optical network and we will study the deterministic conditions for strictly non-blocking Vertical Stacked Optical Benes Networks (VSOBN) with and without worst-case scenarios. We will establish the upper bound on blocking probability of Vertical Stacked Optical Benes Networks with respect to the number of planes used when the non-blocking requirement is not met. We will then study routing in WDM Benes networks and propose a new routing algorithm so that the number of wavelengths can be reduced. Since routing in WDM optical network is an NP-hard problem, many heuristic algorithms are designed by many researchers to perform this routing. We will also develop a genetic algorithm, simulated annealing algorithm and ant colony technique and apply these AI algorithms to route the connections in WDM Benes network

Solving the Corner-Turning Problem for Large Interferometers

The so-called corner turning problem is a major bottleneck for radio telescopes with large numbers of antennas. The problem is essentially that of rapidly transposing a matrix that is too large to store on one single device; in radio interferometry, it occurs because data from each antenna needs to be routed to an array of processors that will each handle a limited portion of the data (a frequency range, say) but requires input from each antenna. We present a low-cost solution allowing the correlator to transpose its data in real time, without contending for bandwidth, via a butterfly network requiring neither additional RAM memory nor expensive general-purpose switching hardware. We discuss possible implementations of this using FPGA, CMOS, analog logic and optical technology, and conclude that the corner turner cost can be small even for upcoming massive radio arrays.Comment: Revised to match accepted MNRAS version. 7 pages, 4 fig

On-board B-ISDN fast packet switching architectures. Phase 1: Study

The broadband integrate services digital network (B-ISDN) is an emerging telecommunications technology that will meet most of the telecommunications networking needs in the mid-1990's to early next century. The satellite-based system is well positioned for providing B-ISDN service with its inherent capabilities of point-to-multipoint and broadcast transmission, virtually unlimited connectivity between any two points within a beam coverage, short deployment time of communications facility, flexible and dynamic reallocation of space segment capacity, and distance insensitive cost. On-board processing satellites, particularly in a multiple spot beam environment, will provide enhanced connectivity, better performance, optimized access and transmission link design, and lower user service cost. The following are described: the user and network aspects of broadband services; the current development status in broadband services; various satellite network architectures including system design issues; and various fast packet switch architectures and their detail designs

A Performance evaluation of several ATM switching architectures

The goal of this thesis is to evaluate the performance of three Asynchronous Transfer Mode switching architectures. After examining many different ATM switching architectures in literature, the three architectures chosen for study were the Knockout switch, the Sunshine switch, and the Helical switch. A discrete-time, event driven system simulator, named ProModel, was used to model the switching behavior of these architectures. Each switching architecture was modeled and studied under at least two design configurations. The performance of the three architectures was then investigated under three different traffic types representative of traffic found in B-ISDN: random, constant bit rate, and bursty. Several key performance parameters were measured and compared between the architectures. This thesis also explored the implementation complexities and fault tolerance of the three selected architectures

Analyzing Traffic and Multicast Switch Issues in an ATM Network.

This dissertation attempts to solve two problems related to an ATM network. First, we consider packetized voice and video sources as the incoming traffic to an ATM multiplexer and propose modeling methods for both individual and aggregated traffic sources. These methods are, then, used to analyze performance parameters such as buffer occupancy, cell loss probability, and cell delay. Results, thus obtained, for different buffer sizes and number of voice and video sources are analyzed and compared with those generated from existing techniques. Second, we study the priority handling feature for time critical services in an ATM multicast switch. For this, we propose a non-blocking copy network and priority handling algorithms. We, then, analyze the copy network using an analytical method and simulation. The analysis utilizes both priority and non-priority cells for two different output reservation schemes. The performance parameters, based on cell delay, delay jitter, and cell loss probability, are studied for different buffer sizes and fan-outs under various input traffic loads. Our results show that the proposed copy network provides a better performance for the priority cells while the performance for the non-priority cells is slightly inferior in comparison with the scenario when the network does not consider priority handling. We also study the fault-tolerant behavior of the copy network, specially for the broadcast banyan network subsection, and present a routing scheme considering the non-blocking property under a specific pattern of connection assignments. A fault tolerant characteristic can be quantified using the full access probability. The computation of the full access probability for a general network is known to be NP-hard. We, therefore, provide a new bounding technique utilizing the concept of minimal cuts to compute full access probability of the copy network. Our study for the fault-tolerant multi-stage interconnection network having either an extra stage or chaining shows that the proposed technique provides tighter bounds as compared to those given by existing approaches. We also apply our bounding method to compute full access probability of the fault-tolerant copy network

Devices and networks for optical switching

This thesis is concerned with some aspects of the application of optics to switching and computing. Two areas are dealt with: the design of switching networks which use optical interconnects, and the development and application of the t-SEED optical logic device. The work on optical interconnects looks at the multistage interconnection network which has been proposed as a hybrid switch using both electronics and optics. It is shown that the architecture can be mapped from one dimensional to two dimensional format, so that the machine makes full use of the space available to the optics. Other mapping rules are described which allow the network to make optimum use of the optical interconnects, and the endpoint is a hybrid optical-electronic machine which should be able to outperform an all-electronic equivalent. The development of the t-SEED optical logic device is described, which is the integration of a phototransistor with a multiple quantum well optical modulator. It is found to be important to have the modulator underneath rather than on top of the transistor to avoid unwanted thyristor action. In order for the transistor to have a high gain the collector must have a low doping level, the exit window in the substrate must be etched all the way to the emitter layer, and the etch must not damage the emitter-base junction. A real optical gain of 1.6 has been obtained, which is higher than has ever been reached before but is not as high as should be possible. Improvements to the device are suggested. A new model of the Fabry-Perot cavity is introduced which helps considerably in the interpretation of experimental measurements made on the quantum well modulators. Also a method of improving the contrast of the multiple quantum well modulator by grading the well widths is proposed which may find application in long wavelength transmission modulators. Some systems which make use of the t-SEED are considered. It is shown that the t-SEED device has the right characteristics for use as a neuron element in the optical implementation of a neural network. A new image processing network for clutter removal in binary images is introduced which uses the t-SEED, and a brief performance analysis suggests that the network may be superior to an all-electronic machine

Design of optical burst switches based on dual shuffle-exchange network and deflection routing.

Choy Man Ting.Thesis (M.Phil.)--Chinese University of Hong Kong, 2003.Includes bibliographical references (leaves 66-69).Abstracts in English and Chinese.Acknowledgments --- p.iiAbstract --- p.vTable of Contents --- p.viiList of figures --- p.viiiChapter Chapter 1 --- p.12Chapter 1.1 --- OBS Network Architecture --- p.3Chapter 1.2 --- Offset Time and Reservation Schemes --- p.5Chapter 1.3 --- Research Objectives --- p.7Chapter 1.4 --- Overview --- p.8Chapter Chapter 2 --- p.9Chapter 2.1 --- WDM crossbar architectures --- p.9Chapter 2.2 --- Switch Based on Optical Crossbars --- p.10Chapter 2.3 --- Switch Based on Wavelength Grating Routers --- p.11Chapter Chapter 3 --- p.14Chapter 3.1 --- Basics of Dual Shuffle Exchange Network --- p.14Chapter 3.2 --- Dual Shuffle-exchange Network --- p.16Chapter 3.3 --- Proposed Architecture based on DSN --- p.19Chapter 3.4 --- Analysis on blocking due to output contention --- p.20Chapter 3.5 --- Implementation issues on the 4x4 switching module --- p.23Chapter 3.6 --- Analysis: Non-blocking versus banyan --- p.25Chapter Chapter 4 --- p.30Chapter 4.1 --- First Scheme --- p.30Chapter 4.2 --- Simulation on the first scheme --- p.33Chapter 4.3 --- Second Scheme: Tunable wavelength converter --- p.37Chapter 4.4 --- Third Scheme: Route to specific wavelength port --- p.42Chapter 4.5 --- Analysis on blocking due to insufficient stages --- p.46Chapter Chapter 5 --- p.49Chapter 5.1 --- Delay analysis of DSN --- p.49Chapter 5.2 --- Vertical Expansion --- p.51Chapter 5.3 --- Simulation results on vertical expansion --- p.52Chapter 5.4 --- Building DSN with 8x8 MEMS switches --- p.54Chapter 5.5 --- Prove of the proposed Quarter shuffle network --- p.56Chapter 5.6 --- Comparison between Quarter shuffle and doubled links approaches --- p.58Chapter Chapter 6 --- p.64Conclusion --- p.64Bibliography --- p.6

Novel techniques in large scaleable ATM switches

Bibliography: p. 172-178.This dissertation explores the research area of large scale ATM switches. The requirements for an ATM switch are determined by overviewing the ATM network architecture. These requirements lead to the discussion of an abstract ATM switch which illustrates the components of an ATM switch that automatically scale with increasing switch size (the Input Modules and Output Modules) and those that do not (the Connection Admission Control and Switch Management systems as well as the Cell Switch Fabric). An architecture is suggested which may result in a scalable Switch Management and Connection Admission Control function. However, the main thrust of the dissertation is confined to the cell switch fabric. The fundamental mathematical limits of ATM switches and buffer placement is presented next emphasising the desirability of output buffering. This is followed by an overview of the possible routing strategies in a multi-stage interconnection network. A variety of space division switches are then considered which leads to a discussion of the hypercube fabric, (a novel switching technique). The hypercube fabric achieves good performance with an O(N.log₂N)²) scaling. The output module, resequencing, cell scheduling and output buffering technique is presented leading to a complete description of the proposed ATM switch. Various traffic models are used to quantify the switch's performance. These include a simple exponential inter-arrival time model, a locality of reference model and a self-similar, bursty, multiplexed Variable Bit Rate (VBR) model. FIFO queueing is simple to implement in an ATNI switch, however, more responsive queueing strategies can result in an improved performance. An associative memory is presented which allows the separate queues in the ATM switch to be effectively logically combined into a single FIFO queue. The associative memory is described in detail and its feasibility is shown by laying out the Integrated Circuit masks and performing an analogue simulation of the IC's performance is SPICE3. Although optimisations were required to the original design, the feasibility of the approach is shown with a 15Ƞs write time and a 160Ƞs read time for a 32 row, 8 priority bit, 10 routing bit version of the memory. This is achieved with 2µm technology, more advanced technologies may result in even better performance. The various traffic models and switch models are simulated in a number of runs. This shows the performance of the hypercube which outperforms a Clos network of equivalent technology and approaches the performance of an ideal reference fabric. The associative memory leverages a significant performance advantage in the hypercube network and a modest advantage in the Clos network. The performance of the switches is shown to degrade with increasing traffic density, increasing locality of reference, increasing variance in the cell rate and increasing burst length. Interestingly, the fabrics show no real degradation in response to increasing self similarity in the fabric. Lastly, the appendices present suggestions on how redundancy, reliability and multicasting can be achieved in the hypercube fabric. An overview of integrated circuits is provided. A brief description of commercial ATM switching products is given. Lastly, a road map to the simulation code is provided in the form of descriptions of the functionality found in all of the files within the source tree. This is intended to provide the starting ground for anyone wishing to modify or extend the simulation system developed for this thesis