SIGNAL PROCESSING TECHNIQUES AND APPLICATIONS

As the technologies scaling down, more transistors can be fabricated into the same area, which enables the integration of many components into the same substrate, referred to as system-on-chip (SoC). The components on SoC are connected by on-chip global interconnects. It has been shown in the recent International Technology Roadmap of Semiconductors (ITRS) that when scaling down, gate delay decreases, but global interconnect delay increases due to crosstalk. The interconnect delay has become a bottleneck of the overall system performance. Many techniques have been proposed to address crosstalk, such as shielding, buffer insertion, and crosstalk avoidance codes (CACs). The CAC is a promising technique due to its good crosstalk reduction, less power consumption and lower area. In this dissertation, I will present analytical delay models for on-chip interconnects with improved accuracy. This enables us to have a more accurate control of delays for transition patterns and lead to a more efficient CAC, whose worst-case delay is 30-40% smaller than the best of previously proposed CACs. As the clock frequency approaches multi-gigahertz, the parasitic inductance of on-chip interconnects has become significant and its detrimental effects, including increased delay, voltage overshoots and undershoots, and increased crosstalk noise, cannot be ignored. We introduce new CACs to address both capacitive and inductive couplings simultaneously.Quantum computers are more powerful in solving some NP problems than the classical computers. However, quantum computers suffer greatly from unwanted interactions with environment. Quantum error correction codes (QECCs) are needed to protect quantum information against noise and decoherence. Given their good error-correcting performance, it is desirable to adapt existing iterative decoding algorithms of LDPC codes to obtain LDPC-based QECCs. Several QECCs based on nonbinary LDPC codes have been proposed with a much better error-correcting performance than existing quantum codes over a qubit channel. In this dissertation, I will present stabilizer codes based on nonbinary QC-LDPC codes for qubit channels. The results will confirm the observation that QECCs based on nonbinary LDPC codes appear to achieve better performance than QECCs based on binary LDPC codes.As the technologies scaling down further to nanoscale, CMOS devices suffer greatly from the quantum mechanical effects. Some emerging nano devices, such as resonant tunneling diodes (RTDs), quantum cellular automata (QCA), and single electron transistors (SETs), have no such issues and are promising candidates to replace the traditional CMOS devices. Threshold gate, which can implement complex Boolean functions within a single gate, can be easily realized with these devices. Several applications dealing with real-valued signals have already been realized using nanotechnology based threshold gates. Unfortunately, the applications using finite fields, such as error correcting coding and cryptography, have not been realized using nanotechnology. The main obstacle is that they require a great number of exclusive-ORs (XORs), which cannot be realized in a single threshold gate. Besides, the fan-in of a threshold gate in RTD nanotechnology needs to be bounded for both reliability and performance purpose. In this dissertation, I will present a majority-class threshold architecture of XORs with bounded fan-in, and compare it with a Boolean-class architecture. I will show an application of the proposed XORs for the finite field multiplications. The analysis results will show that the majority class outperforms the Boolean class architectures in terms of hardware complexity and latency. I will also introduce a sort-and-search algorithm, which can be used for implementations of any symmetric functions. Since XOR is a special symmetric function, it can be implemented via the sort-and-search algorithm. To leverage the power of multi-input threshold functions, I generalize the previously proposed sort-and-search algorithm from a fan-in of two to arbitrary fan-ins, and propose an architecture of multi-input XORs with bounded fan-ins

Network-on-Chip

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems

Synthesis for circuit reliability

textElectrical and Computer Engineerin

Основи схемотехніки електронних систем

Basics of circuitry are stated, principles of operation are considered, it is given calculations of analog, digital and pulse devices of electronic systems, based on semiconductor devices, integrated operational amplifiers and integrated logic circuits of TTL, MOS, CMOS types, construction principles of systems of control by electronics devices based on microprocessors and microcontrollers. For students of institutions of higher education. It can be useful for specialists on electronic engineering, specializing in the area of development, fabrication and maintenance of electronic systems and devices

The design of public transit networks with heuristic algorithms : case study Cape Town

Includes bibliographical references.The Transit Network Design Problem (TNDP) is well-researched in the field of transportation planning. It deals with the design of optimized public transportation networks and systems, and belongs to the class of non-linear optimization problems. In solving the problem, attempts are made to balance the tradeoffs between utility maximization and cost minimization given some resource constraints, within the context of a transportation network. In this dissertation, the design of a public transit network is undertaken and tested for Cape Town. The focus of the research is on obtaining an optimal network configuration that minimizes cost for both users and operators of the network. In doing so, heuristic solution algorithms are implemented in the design process, since they are known to generate better results for non-linear optimization problems than analytical ones. This algorithm which is named a Bus Route Network Design Algorithm (BRNDA) is based on genetic algorithms. Furthermore, it has three key components namely: 1) Bus Route Network Generation Algorithm (BRNGA) - which generates the potential network solutions; 2) Bus Route Network Analysis Procedure (BRNAP) - which evaluates the generated solutions; 3) Bus Route Network Search Algorithm (BRNSA) - which searches for an optimal or near optimal network option, among the feasible ones. The solution approach is tested first on a small scale network to demonstrate its numerical results, then it is applied to a large scale network, namely the Cape Town road network

On Organization of Information: Approach and Early Work

In this report we describe an approach for organizing information for presentation and display. "e approach stems from the observation that there is a stepwise progression in the way signals (from the environment and the system under consideration) are extracted and transformed into data, and then analyzed and abstracted to form representations (e.g., indications and icons) on the user interface. In physical environments such as aerospace and process control, many system components and their corresponding data and information are interrelated (e.g., an increase in a chamber s temperature results in an increase in its pressure). "ese interrelationships, when presented clearly, allow users to understand linkages among system components and how they may affect one another. Organization of these interrelationships by means of an orderly structure provides for the so-called "big picture" that pilots, astronauts, and operators strive for

The Telecommunications and Data Acquisition Progress Report 42-77

Activities in space communication, radio navigation, radio science, and ground-based astronomy are reported. Advanced systems for the Deep Space Network and its Ground-Communications Facility are discussed including station control and system technology. Network sustaining as well as data and information systems are covered. Studies of geodynamics, investigations of the microwave spectrum, and the search for extraterrestrial intelligence are reported

Understanding pedestrian decision-making during the COVID-19 pandemic

Coronavirus Disease 2019 (COVID-19) caused by the SARS-CoV-2 virus became a worldwide global emergency in January 2020 and a worldwide pandemic in March 2020. COVID-19 is a highly contagious respiratory illness that primarily affects the lungs and, in some extreme cases, multiple organs, permanent organ damage and even death. The COVID-19 pandemic, and one of its primary mitigation measures, social distancing, has presented a change in the navigation of public walking spaces. In addition, measures have been put in place to reduce exposure to the disease. Generally, these efforts included recommendations to wear face masks if social distancing cannot be maintained, and at times the closure of schools, offices, businesses, and other non-essential establishments. As a result of restrictions and to encourage the maintenance of mental and physical health, public health officials have encouraged activities, such as walking outside, while maintaining a physical distance of two metres from others. Despite a large amount of research conducted on public health aspects of COVID-19, very little has been focused on the impact on pedestrians and potential changes in behaviour due to COVID-19 related recommendations for social distancing. Moreover, little research has been done on how pedestrian mental models generally develop. A mixed-method study, employing a survey and semi-structured interviews, was conducted to explore the development of pedestrian mental models within the context of following social distancing measures. The objective of the thesis research study was to discover any new walking rules and mental models that adult pedestrians within the Waterloo Region of Ontario, Canada, are using as they navigate in outdoor public spaces, with social distancing measures in place. The research study was conducted in two phases: Phase I (survey) and II (semi-structured interview), with the results of Phase I informing the direction of Phase II. The emerging mental models, rules, impacts, and changes experienced by adult pedestrians in the Waterloo Region are presented. New rules that pedestrians are using can be categorized into navigating public spaces, crowded places, and locations with strangers. The results of the survey and emerging rules suggest that pedestrians are experiencing a higher level of risk awareness when walking outdoors. The results of this study indicate that adult pedestrians are now adjusting their walking habits and rules when walking in outdoor, public spaces in response to COVID-19-related social distancing measures. Based on reported actions to be taken for walking scenarios and emerging rules, pedestrians dynamically consider risk to self and risk to others when walking in public areas. Infrastructure was also noted as an important aspect of determining what action to take by pedestrians to create or maintain social distance. Recommendations related to changes in infrastructure, including wider sidewalks and pedestrian-friendly streets, and strategies for public education are discussed