CMOS SPADs selection, modeling and characterization towards image sensors implementation

The selection, modeling and characterization of Single Photon Avalanche Diodes (SPADs) are presented. Working with the standard 180nm UMC CMOS process, different SPAD structures are proposed in combination with several quenching circuits in order to compare their relative performances. Various configurations for the active region and the prevention of the premature edge breakdown are tested, looking for a miniaturization of the devices to implement image sensor arrays without loses in their performance

CMOS current-mode chaotic neurons

This paper presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural networks, and another circuit to realize programmable current-mode synapse using CMOS-compatible BJT's. They have been fabricated in a double-metal, single-poly 1.6 /spl mu/m CMOS technology and their measured performance reached the expected function and specifications. The neuron soma circuits use a novel, highly accurate CMOS circuit strategy to realize piecewise-linear characteristics in the current-mode domain. Their prototypes obtain reduced area and low voltage power supply (down to 3 V) with clock frequency of 500 kHz. As regard to the synapse circuit, it obtains large linearity and continuous, linear, weight adjustment by exploration of the exponential-law operation of CMOS-BJT's. The full accordance observed between theory and measurements supports the development of future analog VLSI chaotic neural networks to emulate biological systems and advanced computation

CMOS circuit implementations for neuron models

The mathematical neuron basic cells used as basic cells in popular neural network architectures and algorithms are discussed. The most popular neuron models (without training) used in neural network architectures and algorithms (NNA) are considered, focusing on hardware implementation of neuron models used in NAA, and in emulation of biological systems. Mathematical descriptions and block diagram representations are utilized in an independent approach. Nonoscillatory and oscillatory models are discusse

Design of Adiabatic MTJ-CMOS Hybrid Circuits

Low-power designs are a necessity with the increasing demand of portable devices which are battery operated. In many of such devices the operational speed is not as important as battery life. Logic-in-memory structures using nano-devices and adiabatic designs are two methods to reduce the static and dynamic power consumption respectively. Magnetic tunnel junction (MTJ) is an emerging technology which has many advantages when used in logic-in-memory structures in conjunction with CMOS. In this paper, we introduce a novel adiabatic hybrid MTJ/CMOS structure which is used to design AND/NAND, XOR/XNOR and 1-bit full adder circuits. We simulate the designs using HSPICE with 32nm CMOS technology and compared it with a non-adiabatic hybrid MTJ/CMOS circuits. The proposed adiabatic MTJ/CMOS full adder design has more than 7 times lower power consumtion compared to the previous MTJ/CMOS full adder

CMOS-3D smart imager architectures for feature detection

This paper reports a multi-layered smart image sensor architecture for feature extraction based on detection of interest points. The architecture is conceived for 3-D integrated circuit technologies consisting of two layers (tiers) plus memory. The top tier includes sensing and processing circuitry aimed to perform Gaussian filtering and generate Gaussian pyramids in fully concurrent way. The circuitry in this tier operates in mixed-signal domain. It embeds in-pixel correlated double sampling, a switched-capacitor network for Gaussian pyramid generation, analog memories and a comparator for in-pixel analog-to-digital conversion. This tier can be further split into two for improved resolution; one containing the sensors and another containing a capacitor per sensor plus the mixed-signal processing circuitry. Regarding the bottom tier, it embeds digital circuitry entitled for the calculation of Harris, Hessian, and difference-of-Gaussian detectors. The overall system can hence be configured by the user to detect interest points by using the algorithm out of these three better suited to practical applications. The paper describes the different kind of algorithms featured and the circuitry employed at top and bottom tiers. The Gaussian pyramid is implemented with a switched-capacitor network in less than 50 μs, outperforming more conventional solutions.Xunta de Galicia 10PXIB206037PRMinisterio de Ciencia e Innovación TEC2009-12686, IPT-2011-1625-430000Office of Naval Research N00014111031

Cryogenic Characterization of 180 nm CMOS Technology at 100 mK

Conventional CMOS technology operated at cryogenic conditions has recently attracted interest for its uses in low-noise electronics. We present one of the first characterizations of 180 nm CMOS technology at a temperature of 100 mK, extracting I/V characteristics, threshold voltages, and transconductance values, as well as observing their temperature dependence. We find that CMOS devices remain fully operational down to these temperatures, although we observe hysteresis effects in some devices. The measurements described in this paper can be used to inform the future design of CMOS devices intended to be operated in this deep cryogenic regime

Digital Detection of Oxide Breakdown and Life-Time Extension in Submicron CMOS Technology

An approach is introduced to extend the lifetime of high-voltage analog circuits in CMOS technologies based on redundancy, like that known for DRAMS. A large power transistor is segmented into N smaller ones in parallel. If a sub-transistor is broken, it is removed automatically from the compound transistor. The principleis demonstrated in an RF CMOS Power Amplifier (PA) in standard 1.2V 90nm CMOS

Development of high-performances monolithic CMOS detectors for space applications

This paper describes the development of a 750x750 pixels CMOS image sensor for star tracker applications. A first demonstrator of such a star tracker called SSM star tracker built around a 512x512 detector has been recently developed and proves the feasibility of such instrument. In order to take fully advantage of the CMOS image sensor step, the 750x750 device called SSM CMOS detector which will take part of the final star tracker, can be considered as a major technical breakthrough that gives a decisive advantage in terms of on satellite implementation cost and flexibility (sensor mass and power consumption minimisation, electronics and architecture flexibility). Indeed, built using the 0.5μm Alcatel Microelectronics standard CMOS technology, the SSM CMOS detector will feature on-chip temperature sensor and on-chip sequencer. In order to evaluate the radiation tolerance of such manufacturing technology, a radiation campaign that contains studies of total dose and latch-up effects has been led on a specific test vehicle