Real-time 100-GS/s sigma-delta modulator for all-digital radio-over-fiber transmission

All-digital radio-over-fiber (RoF) transmission has attracted a significant amount of interest in digital-centric systems or centralized networks because it greatly simplifies the front-end hardware by using digital processing. The sigma-delta modulator (SDM)-based all-digital RoF approach pushes the digital signal processing as far as possible into the transmit chain. We present a real-time 100-GS/s fourth-order single-bit SDM for all-digital RoF transmission in the high-frequency band without the aid of analog/optical up-conversion. This is the fastest sigma-delta modulator reported and this is also the first real-time demonstration of sigma-delta-modulated RoF in the frequency band above 24 GHz. 4.68 Gb/s (2.34 Gb/s) 64-QAM is transported over 10-km standard single-mode fiber in the C-band with 6.46% (4.73%) error vector magnitude and 3.13 Gb/s 256-QAM can be even received in an optical back-to-back configuration. The carrier frequency can be digitally tuned at run-time, covering a wide frequency range from 22.75 to 27.5 GHz. Besides, this high-speed sigma-delta modulator introduces less than 1 mu s latency in the transmit chain. Its all-digital nature enables network virtualization, making the transmitter compatible with different existing standards. The prominent performance corroborates the strong competitiveness of this SDM-based RoF approach in high-frequency RoF 5C communication

Novel Multicarrier Memory Channel Architecture Using Microwave Interconnects: Alleviating the Memory Wall

abstract: The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon. A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel. Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Ropeway roller batteries dynamics. Modeling, identification, and full-scale validation

A parametric mechanical model based on a Lagrangian formulation is here proposed to predict the dynamic response of roller batteries during the vehicles transit across the so-called compression towers in ropeways transportation systems. The model describes the dynamic interaction between the ropeway substructures starting from the modes and frequencies of the system to the forced dynamic response caused by the vehicles transit. The analytical model is corroborated and validated via an extensive experimental campaign devoted to the dynamic characterization of the roller battery system. The data acquired on site via a custom-design sensor network allowed to identify the frequencies and damping ratios by employing the Frequency Domain Decomposition (FDD) method. The high fidelity modeling and the system identification procedure are discussed

Clock Synchronization in Wireless Sensor Networks: An Overview

The development of tiny, low-cost, low-power and multifunctional sensor nodes equipped with sensing, data processing, and communicating components, have been made possible by the recent advances in micro-electro-mechanical systems (MEMS) technology. Wireless sensor networks (WSNs) assume a collection of such tiny sensing devices connected wirelessly and which are used to observe and monitor a variety of phenomena in the real physical world. Many applications based on these WSNs assume local clocks at each sensor node that need to be synchronized to a common notion of time. This paper reviews the existing clock synchronization protocols for WSNs and the methods of estimating clock offset and clock skew in the most representative clock synchronization protocols for WSNs