A low-speed BIST framework for high-performance circuit testing

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addresse

Regression modeling for digital test of ΣΔ modulators

The cost of Analogue and Mixed-Signal circuit testing is an important bottleneck in the industry, due to timeconsuming verification of specifications that require state-ofthe- art Automatic Test Equipment. In this paper, we apply the concept of Alternate Test to achieve digital testing of converters. By training an ensemble of regression models that maps simple digital defect-oriented signatures onto Signal to Noise and Distortion Ratio (SNDR), an average error of 1:7% is achieved. Beyond the inference of functional metrics, we show that the approach can provide interesting diagnosis information.Ministerio de Educación y Ciencia TEC2007-68072/MICJunta de Andalucía TIC 5386, CT 30

Circuits and circuit testing for spaceborne redundant digital systems Special technical report no. 3

Design and testing of majority logic redundancy for spaceborne and GSE digital system

Reasoning and Improving on Software Resilience against Unanticipated Exceptions

In software, there are the errors anticipated at specification and design time, those encountered at development and testing time, and those that happen in production mode yet never anticipated. In this paper, we aim at reasoning on the ability of software to correctly handle unanticipated exceptions. We propose an algorithm, called short-circuit testing, which injects exceptions during test suite execution so as to simulate unanticipated errors. This algorithm collects data that is used as input for verifying two formal exception contracts that capture two resilience properties. Our evaluation on 9 test suites, with 78% line coverage in average, analyzes 241 executed catch blocks, shows that 101 of them expose resilience properties and that 84 can be transformed to be more resilient

Low-Power In-Circuit testing of a LNA

A new technique is proposed to tackle in-circuit testing of embedded RF blocks. It relies on observing the cross-correlation between its output voltage and power supply current, using a translinear cross-correlator circuit. Although a structural test is performed, simulation results show that fault detection criteria can be established based on acceptable deviations of performance characterization parameters. The case of a Low Noise Amplifier is presented

Circuit Testing Based on Fuzzy Sampling with BDD Bases

Fuzzy testing of integrated circuits is an established technique. Current approaches generate an approximately uniform random sample from a translation of the circuit to Boolean logic. These approaches have serious scalability issues, which become more pressing with the ever-increasing size of circuits. We propose using a base of binary decision diagrams to sample the translations as a soft computing approach. Uniformity is guaranteed by design and scalability is greatly improved. We test our approach against five other state-of-the-art tools and find our tool to outperform all of them, both in terms of performance and scalability

Automatic Test Pattern Generation for Robust Quantum Circuit Testing

Quantum circuit testing is essential for detecting potential faults in realistic quantum devices, while the testing process itself also suffers from the inexactness and unreliability of quantum operations. This paper alleviates the issue by proposing a novel framework of automatic test pattern generation (ATPG) for the robust quantum circuit testing. We introduce the stabilizer projector decomposition (SPD) for representing the quantum test pattern, and construct the test application using Clifford-only circuits, which are rather robust and efficient as evidenced in the fault-tolerant quantum computation. However, it is generally hard to generate SPDs due to the exponentially growing number of the stabilizer projectors. To circumvent this difficulty, we develop an SPD generation algorithm, as well as several acceleration techniques which can exploit both locality and sparsity in generating SPDs. The effectiveness of our algorithms are validated by 1) theoretical guarantees under reasonable conditions, 2) experimental results on commonly used benchmark circuits, such as Quantum Fourier Transform (QFT), Quantum Volume (QV) and Bernstein-Vazirani (BV) in IBM Qiskit. For example, test patterns are automatically generated by our algorithm for a 10-qubit QFT circuit, and then a fault is detected by simulating the test application with detection accuracy higher than 91%.Comment: 18 pages, 6 figures, 3 table