On Energy Efficiency of Switched-Capacitor Converters

published_or_final_versio

An Input Power-Aware Maximum Efficiency Tracking Technique for Energy Harvesting in IoT Applications

The Internet of Things (IoT) enables intelligent monitoring and management in many applications such as industrial and biomedical systems as well as environmental and infrastructure monitoring. As a result, IoT requires billions of wireless sensor network (WSN) nodes equipped with a microcontroller and transceiver. As many of these WSN nodes are off-grid and small-sized, their limited-capacity batteries need periodic replacement. To mitigate the high costs and challenges of these battery replacements, energy harvesting from ambient sources is vital to achieve energy-autonomous operation. Energy harvesting for WSNs is challenging because the available energy varies significantly with ambient conditions and in many applications, energy must be harvested from ultra-low power levels. To tackle these stringent power constraints, this dissertation proposes a discontinuous charging technique for switched-capacitor converters that improves the power conversion efficiency (PCE) at low input power levels and extends the input power harvesting range at which high PCE is achievable. Discontinuous charging delivers current to energy storage only during clock non-overlap time. This enables tuning of the output current to minimize converter losses based on the available input power. Based on this fundamental result, an input power-aware, two-dimensional efficiency tracking technique for WSNs is presented. In addition to conventional switching frequency control, clock nonoverlap time control is introduced to adaptively optimize the power conversion efficiency according to the sensed ambient power levels. The proposed technique is designed and simulated in 90nm CMOS with post-layout extraction. Under the same input and output conditions, the proposed system maintains at least 45% PCE at 4μW input power, as opposed to a conventional continuous system which requires at least 18.7μW to maintain the same PCE. In this technique, the input power harvesting range is extended by 1.5x. The technique is applied to a WSN implementation utilizing the IEEE 802.15.4- compatible GreenNet communications protocol for industrial and wearable applications. This allows the node to meet specifications and achieve energy autonomy when deployed in harsher environments where the input power is 49% lower than what is required for conventional operation

Integrated charge pump voltage multiplier regulator for high current applications

Orientadores: Jacobus Willibrordus Swart, Jader Alves de Lima FilhoDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de ComputaçãoResumo: Neste trabalho de Mestrado, foi projetado um conversor DC/DC charge-pump (CP) duplicador de tensão para corrente de carga máxima de 20mA, e que necessita de circuitos de controle para o apropriado acionamento das chaves, regulação de tensão e proteção do estágio duplicador de tensão. O sistema de controle projetado é composto por um circuito de regulação linear (CRL), um regulador Skip, um limitador de corrente (LC) e um circuito de bootstrapping (BOOT) que auxilia o acionamento do estágio duplicador. CP corresponde ao estágio de potência do sistema que faz interface direta com a carga, sendo sua tensão de entrada (PVIN) nominal no valor de 1,5V. O trabalho objetiva obter um conversor DC/DC funcional (demonstrado por resultados de Silício) atingindo resultados experimentais com o menor desvio possível comparados aos valores simulados durante o projeto. A tensão simulada de saída (VOUT), a vazio (sem carga), é 3V. Para carga máxima DC (20mA), o valor de VOUT simulado é de 2,4V. O circuito BOOT gera uma tensão na faixa de 4,5V - 5V, para uma carga DC de 1mA. A corrente limitada pelo bloco LC no circuito duplicador é 30mA. O CLR gera uma tensão inversamente proporcional a VOUT, tendo seus limites mínimo e máximo de 1,3V e 5,2V, respectivamente. Todo o sistema foi integrado no processo de fabricação AMS 0.35um HV, exceto os capacitores do estágio duplicador e do circuito de bootstrapping que são externos. Os resultados experimentais mostram desvio (comparados com simulação) de -12,5% em VOUT @ 20mA DC e -0,13% sem carga, -6% à saída de BOOT @ 1mA DC, +23% CLR mínimo, -3,85% em CRL máximo e +10% na corrente limitada. Durante o desenvolvimento deste trabalho, o Circuito de Regulação Linear (CRL) foi publicado no SBCCI 2009 apresentando sua rápida resposta à transientes de carga, o que é sua grande vantagem comparado a circuitos anteriormente propostosAbstract: In this work, a DC/DC charge-pump voltage-doubler converter, for maximum load current of 20mA, was designed and fabricated. The Charge Pump (CP) needs control circuits for properly switching, voltage regulation and protection of voltage doubler stage. The control system designed comprises a linear regulation circuit (CRL), a Skip mode regulator, current limitation circuit (LC) and a bootstrapping circuit (BOOT), which provides the appropriate voltage to turn on CP power transistors. The voltage doubler is the power stage that interfaces directly to the load and its nominal input voltage PVIN is 1.5V. The objective of this work is to guarantee that the proposed DC/DC converter works properly (proved by Silicon results) and to achieve experimental results with the least deviation possible compared to simulation. The nominal output voltage (VOUT) with no load is 3V. For maximum DC load (20mA), simulated VOUT is 2.4V. BOOT circuit provides voltage within 4.5V - 5V for DC current load of 1mA. The LC limits the drawn current through the voltage-doubler at 30mA. The CRL provides a control voltage inversely proportional to VOUT and its minimum and maximum are 1.3V and 5.2V respectively. The whole system has been integrated in AMS 0.35um HV except the capacitors of CP and BOOT circuits. The experimental results show deviation (comparing to simulation) of -12,5% on VOUT @ 20mA DC and -0,13% @ no load , -6% on BOOT output @ 1mA DC, +23% CLR minimum, -3,85% CRL maximum and +10% on LC circuit. During the development of this work, the CRL circuit has been published in the SBCCI 2009 conference to present its fast-response to stringent load transient which is the biggest CRL advantage compared to previously proposed circuitsMestradoMestre em Engenharia Elétric

High-Efficiency Self-Adjusting Switched Capacitor DC-DC Converter with Binary Resolution

Switched-Capacitor Converters (SCC) suffer from a fundamental power loss deficiency which make their use in some applications prohibitive. The power loss is due to the inherent energy dissipation when SCC operate between or outside their output target voltages. This drawback was alleviated in this work by developing two new classes of SCC providing binary and arbitrary resolution of closely spaced target voltages. Special attention is paid to SCC topologies of binary resolution. Namely, SCC systems that can be configured to have a no-load output to input voltage ratio that is equal to any binary fraction for a given number of bits. To this end, we define a new number system and develop rules to translate these numbers into SCC hardware that follows the algebraic behavior. According to this approach, the flying capacitors are automatically kept charged to binary weighted voltages and consequently the resolution of the target voltages follows a binary number representation and can be made higher by increasing the number of capacitors (bits). The ability to increase the number of target voltages reduces the spacing between them and, consequently, increases the efficiency when the input varies over a large voltage range. The thesis presents the underlining theory of the binary SCC and its extension to the general radix case. Although the major application is in step-down SCC, a simple method to utilize these SCC for step-up conversion is also described, as well as a method to reduce the output voltage ripple. In addition, the generic and unified model is strictly applied to derive the SCC equivalent resistor, which is a measure of the power loss. The theoretical predictions are verified by simulation and experimental results

Radio frequency energy harvesting for autonomous systems

A thesis submitted to the University of Bedfordshire in partial fulfilment of the requirements for the degree of Doctor of PhilosophyRadio Frequency Energy Harvesting (RFEH) is a technology which enables wireless power delivery to multiple devices from a single energy source. The main components of this technology are the antenna and the rectifying circuitry that converts the RF signal into DC power. The devices which are using Radio Frequency (RF) power may be integrated into Wireless Sensor Networks (WSN), Radio Frequency Identification (RFID), biomedical implants, Internet of Things (IoT), Unmanned Aerial Vehicles (UAVs), smart meters, telemetry systems and may even be used to charge mobile phones. Aside from autonomous systems such as WSNs and RFID, the multi-billion portable electronics market – from GSM phones to MP3 players – would be an attractive application for RF energy harvesting if the power requirements are met. To investigate the potential for ambient RFEH, several RF site surveys were conducted around London. Using the results from these surveys, various harvesters were designed and tested for different frequency bands from the RF sources with the highest power density within the Medium Wave (MW), ultra- and super-high (UHF and SHF) frequency spectrum. Prototypes were fabricated and tested for each of the bands and proved that a large urban area around Brookmans park radio centre is suitable location for harvesting ambient RF energy. Although the RFEH offers very good efficiency performance, if a single antenna is considered, the maximum power delivered is generally not enough to power all the elements of an autonomous system. In this thesis we present techniques for optimising the power efficiency of the RFEH device under demanding conditions such as ultra-low power densities, arbitrary polarisation and diverse load impedances. Subsequently, an energy harvesting ferrite rod rectenna is designed to power up a wireless sensor and its transmitter, generating dedicated Medium Wave (MW) signals in an indoor environment. Harvested power management, application scenarios and practical results are also presented

Charge redistribution loss consideration in optimal charge pump design

Charge redistribution loss of capacitors is reviewed, and then employed in the optimal capacitor assignment of charge pumps. The average output voltage is unambiguously defined, and efficiency due to redistribution loss is discussed. Analyses are confirmed by Hspice simulations on charge pumps designed using a 0.35 mu CMOS process

Power Management ICs for Internet of Things, Energy Harvesting and Biomedical Devices

This dissertation focuses on the power management unit (PMU) and integrated circuits (ICs) for the internet of things (IoT), energy harvesting and biomedical devices. Three monolithic power harvesting methods are studied for different challenges of smart nodes of IoT networks. Firstly, we propose that an impedance tuning approach is implemented with a capacitor value modulation to eliminate the quiescent power consumption. Secondly, we develop a hill-climbing MPPT mechanism that reuses and processes the information of the hysteresis controller in the time-domain and is free of power hungry analog circuits. Furthermore, the typical power-performance tradeoff of the hysteresis controller is solved by a self-triggered one-shot mechanism. Thus, the output regulation achieves high-performance and yet low-power operations as low as 12 µW. Thirdly, we introduce a reconfigurable charge pump to provide the hybrid conversion ratios (CRs) as 1⅓× up to 8× for minimizing the charge redistribution loss. The reconfigurable feature also dynamically tunes to maximum power point tracking (MPPT) with the frequency modulation, resulting in a two-dimensional MPPT. Therefore, the voltage conversion efficiency (VCE) and the power conversion efficiency (PCE) are enhanced and flattened across a wide harvesting range as 0.45 to 3 V. In a conclusion, we successfully develop an energy harvesting method for the IoT smart nodes with lower cost, smaller size, higher conversion efficiency, and better applicability. For the biomedical devices, this dissertation presents a novel cost-effective automatic resonance tracking method with maximum power transfer (MPT) for piezoelectric transducers (PT). The proposed tracking method is based on a band-pass filter (BPF) oscillator, exploiting the PT’s intrinsic resonance point through a sensing bridge. It guarantees automatic resonance tracking and maximum electrical power converted into mechanical motion regardless of process variations and environmental interferences. Thus, the proposed BPF oscillator-based scheme was designed for an ultrasonic vessel sealing and dissecting (UVSD) system. The sealing and dissecting functions were verified experimentally in chicken tissue and glycerin. Furthermore, a combined sensing scheme circuit allows multiple surgical tissue debulking, vessel sealer and dissector (VSD) technologies to operate from the same sensing scheme board. Its advantage is that a single driver controller could be used for both systems simplifying the complexity and design cost. In a conclusion, we successfully develop an ultrasonic scalpel to replace the other electrosurgical counterparts and the conventional scalpels with lower cost and better functionality

A Charge-Recycling Scheme and Ultra Low Voltage Self-Startup Charge Pump for Highly Energy Efficient Mixed Signal Systems-On-A-Chip

The advent of battery operated sensor-based electronic systems has provided a pressing need to design energy-efficient, ultra-low power integrated circuits as a means to improve the battery lifetime. This dissertation describes a scheme to lower the power requirement of a digital circuit through the use of charge-recycling and dynamic supply-voltage scaling techniques. The novel charge-recycling scheme proposed in this research demonstrates the feasibility of operating digital circuits using the charge scavenged from the leakage and dynamic load currents inherent to digital design. The proposed scheme efficiently gathers the “ground-bound” charge into storage capacitor banks. This reclaimed charge is then subsequently recycled to power the source digital circuit. The charge-recycling methodology has been implemented on a 12-bit Gray-code counter operating at frequencies of less than 50 MHz. The circuit has been designed in a 90-nm process and measurement results reveal more than 41% reduction in the average energy consumption of the counter. The total energy savings including the power consumed for the generation of control signals aggregates to an average of 23%. The proposed methodology can be applied to an existing digital path without any design change to the circuit but with only small loss to the performance. Potential applications of this scheme are described, specifically in wide-temperature dynamic power reduction and as a source for energy harvesters. The second part of this dissertation deals with the design and development of a self-starting, ultra-low voltage, switched-capacitor (SC) DC-DC converter that is essential to an energy harvesting system. The proposed charge-pump based SC-converter operates from 125-mV input and thus enables battery-less operation in ultra-low voltage energy harvesters. The charge pump does not require any external components or expensive post-fabrication processing to enable low-voltage operation. This design has been implemented in a 130-nm CMOS process. While the proposed charge pump provides significant efficiency enhancement in energy harvesters, it can also be incorporated within charge recycling systems to facilitate adaptable charge-recycling levels. In total, this dissertation provides key components needed for highly energy-efficient mixed signal systems-on-a-chip

A low power signal front-end for passive UHF RFID transponders with a new clock recovery circuit.

Chan, Chi Fat.Thesis (M.Phil.)--Chinese University of Hong Kong, 2009.Includes bibliographical references.Abstracts in English and Chinese.Abstract --- p.2摘要 --- p.5Acknowledgement --- p.7Table of Contents --- p.9List of Figures --- p.11List of Tables --- p.14Chapter 1. --- Introduction --- p.15Chapter 1.2. --- Research Objectives --- p.16Chapter 1.3. --- Thesis Organization --- p.18Chapter 1.4. --- References --- p.19Chapter 2. --- Overview of Passive UHF RFID Transponders --- p.20Chapter 2.1. --- Types of RFID Transponders and Design Challenges of Passive RFID Transponder --- p.20Chapter 2.2. --- Selection of Carrier Frequency --- p.22Chapter 2.3. --- Description of Transponder Construction --- p.22Chapter 2.3.1. --- Power-Generating Circuits --- p.23Chapter 2.3.2. --- Base Band Processor --- p.28Chapter 2.3.3. --- Signal Front-End --- p.29Chapter 2.4. --- Summary --- p.30Chapter 2.5. --- References --- p.31Chapter 3. --- ASK Demodulator for EPC C-l G-2 Transponder --- p.32Chapter 3.1. --- ASK Demodulator Design Considerations --- p.32Chapter 3.1.1. --- Recovered Envelope Distortion --- p.32Chapter 3.1.2. --- Input Power Level Considerations --- p.34Chapter 3.1.3. --- Input RF power Intercepted by ASK Demodulator --- p.36Chapter 3.2. --- ASK Demodulator Design From [3-4] --- p.36Chapter 3.2.1. --- Envelope Waveform Recovery Design --- p.37Chapter 3.2.1.1. --- Voltage Multiplier Branch for Generating Venv --- p.39Chapter 3.2.1.2. --- Voltage Multiplier Branch for Generating Vref --- p.41Chapter 3.2.2. --- Design Considerations for Sensitivity of ASK Demodulator --- p.41Chapter 3.2.3. --- RF Input Power Sharing with Voltage Multiplier --- p.44Chapter 3.2.4. --- ASK Demodulator and Voltage Multiplier Integrated Estimations for Maximum RF Power Input --- p.47Chapter 3.2.5. --- Measurement result and Discussion --- p.49Chapter 3.3. --- Proposed Envelope Detector Circuit --- p.52Chapter 3.3.1. --- Sensitivity Estimation --- p.52Chapter 3.3.2. --- Maximum Tolerable Input Power Estimation --- p.53Chapter 3.3.3. --- Envelope Waveform Recovery of the Proposed Envelope Detector --- p.54Chapter 3.4. --- Summary --- p.57Chapter 3.5. --- References --- p.58Chapter 4. --- Clock Generator for EPC C-l G-2 Transponder --- p.59Chapter 4.1. --- Design Challenges Overview of Clock Generator --- p.59Chapter 4.2. --- Brief Review of PIE Symbols in EPC C1G2 Standard --- p.62Chapter 4.3. --- Proposed Clock Recovery Circuit Based on PIE Symbols for Clock Frequency Calibration --- p.64Chapter 4.3.1. --- Illustration on PIE Symbols for Clock Frequency Calibration --- p.64Chapter 4.3.2. --- Symbol time-length counter --- p.72Chapter 4.3.3. --- The M2.56MHZ Reference Generator and Sampling Frequency Requirement --- p.75Chapter 4.3.4. --- Symbol Length Reconfiguration for Different Tari and FLL Stability --- p.80Chapter 4.3.5. --- Frequency Detector and Loop Filter --- p.83Chapter 4.3.6. --- Proposed DCO Design --- p.84Chapter 4.3.7. --- Measurement Results and Discussions --- p.88Chapter 4.3.7.1. --- Frequency Calibration Measurement Results --- p.89Chapter 4.3.7.2. --- Number x and Tari Variation --- p.92Chapter 4.3.7.3. --- Temperature and Supply Variation --- p.93Chapter 4.3.7.4. --- Transient Supply Variation --- p.94Chapter 4.3.8. --- Works Comparison --- p.95Chapter 4.4. --- Clock Generator with Embedded PIE Decoder --- p.96Chapter 4.4.1. --- Clock Generator for Transponder Review --- p.96Chapter 4.4.2. --- PIE Decoder Review --- p.97Chapter 4.4.3. --- Proposed Clock Generator with Embedded PIE Decoder --- p.97Chapter 4.4.4. --- Measurement Results and Discussions --- p.100Chapter 4.5. --- Summary --- p.103Chapter 4.6. --- References --- p.105Chapter 5. --- ASK Modulator --- p.107Chapter 5.1. --- Introduction to ASK Modulator in RFD Transponder --- p.107Chapter 5.2. --- ASK Modulator Design --- p.109Chapter 5.3. --- ASK Modulator Measurement --- p.110Chapter 5.4. --- Summary --- p.113Chapter 5.5. --- References --- p.113Chapter 6. --- Conclusions --- p.114Chapter 6.1. --- Contribution --- p.114Chapter 6.2. --- Future Development --- p.11

Power Management Circuits for Energy Harvesting Applications

Energy harvesting is the process of converting ambient available energy into usable electrical energy. Multiple types of sources are can be used to harness environmental energy: solar cells, kinetic transducers, thermal energy, and electromagnetic waves. This dissertation proposal focuses on the design of high efficiency, ultra-low power, power management units for DC energy harvesting sources. New architectures and design techniques are introduced to achieve high efficiency and performance while achieving maximum power extraction from the sources. The first part of the dissertation focuses on the application of inductive switching regulators and their use in energy harvesting applications. The second implements capacitive switching regulators to minimize the use of external components and present a minimal footprint solution for energy harvesting power management. Analysis and theoretical background for all switching regulators and linear regulators are described in detail. Both solutions demonstrate how low power, high efficiency design allows for a self-sustaining, operational device which can tackle the two main concerns for energy harvesting: maximum power extraction and voltage regulation. Furthermore, a practical demonstration with an Internet of Things type node is tested and positive results shown by a fully powered device from harvested energy. All systems were designed, implemented and tested to demonstrate proof-of-concept prototypes