Power distribution design for high-density packages

This thesis describes the design of a high-density power distribution system. Properties of impedances of power distribution systems are examined. Impedances are classified as self and trans-impedances. These properties are then used to save simulation time, which is a big factor for power distribution system design. Time domain models are extracted for the test cases. A novel 2D-3D technique of placing decoupling capacitors is demonstrated that is based on the effectiveness of the capacitor at that location. The power distribution system acts as a cavity resonator supporting discrete modes that vary with distance. Each capacitor is placed at the physical location where it has maximum impact on corresponding system modes. Targeting the modes at the ports where they are dominant using decoupling capacitors reduces trans-impedances. This technique is extended to the entire surface of the power distribution system using just a single set of simulations. This thesis presents a novel 2D-3D approach of designing high-density boards having chips with multiple power connections without having to go through lengthy tedious simulations

Models predicting the performance of IC component or PCB channel during electromagnetic interference

This dissertation is composed of three papers, which cover the prediction of the characteristics of jitter due to crosstalk and due to simultaneous switching noise, and covers susceptibility of delay locked loop (DLL) to electromagnetic interference. In the first paper, an improved tail-fit de-convolution method is proposed for characterizing the impact of deterministic jitter in the presence of random jitter. A Wiener filter de-convolution method is also presented for extracting the characteristics of crosstalk induced jitter from measurements of total jitter made when the crosstalk sources were and were not present. The proposed techniques are shown to work well both in simulations and in measurements of a high-speed link. In the second paper, methods are developed to predict the statistical distribution of timing jitter due to dynamic currents drawn by an integrated circuit (IC) and the resulting power supply noise on the PCB. Distribution of dynamic currents is found through vectorless methods. Results demonstrate the approach can rapidly determine the average and standard deviation of the power supply noise voltage and the peak jitter within 5~15% error, which is more than sufficient for predicting the performance impact on integrated circuits. In the third paper, a model is developed to predict the susceptibility of a DLL to electromagnetic noise on the power supply. With the proposed analytical noise transfer function, peak to peak jitter and cycle to cycle jitter at the DLL output can be estimated, which can be use to predict when soft failures will occur and to better understand how to fix these failures. Simulation and measurement results demonstrate the accuracy of the DLL delay model. --Abstract, page iv

Study to investigate and evaluate means of optimizing the Ku-band communication function for the space shuttle

The forward link of the overall Ku-band communication system consists of the ground- TDRS-orbiter communication path. Because the last segment of the link is directed towards a relatively low orbiting shuttle, a PN code is used to reduce the spectral density. A method is presented for incorporating code acquisition and tracking functions into the orbiter's Ku-band receiver. Optimization of a three channel multiplexing technique is described. The importance of Costas loop parameters to provide false lock immunity for the receiver, and the advantage of using a sinusoidal subcarrier waveform, rather than square wave, are discussed

A GHz-range, High-resolution Multi-modulus Prescaler for Extreme Environment Applications

The generation of a precise, low-noise, reliable clock source is critical to developing mixed-signal and digital electronic systems. The applications of such a clock source are greatly expanded if the clock source can be configured to output different clock frequencies. The phase-locked loop (PLL) is a well-documented architecture for realizing this configurable clock source. Principle to the configurability of a PLL is a multi-modulus divider. The resolution of this divider (or prescaler) dictates the resolution of the configurable PLL output frequency. In integrated PLL designs, such a multi-modulus prescaler is usually sourced from a GHz-range voltage-controlled oscillator. Therefore, a fully-integrated PLL ASIC requires the development of a high-speed, high-resolution multi-modulus prescaler. The design challenges associated with developing such a prescaler are compounded when the application requires the device to operate in an extreme environment. In these extreme environments (often extra-terrestrial), wide temperature ranges and radiation effects can adversely affect the operation of electronic systems. Even more problematic is that extreme temperatures and ionizing radiation can cause permanent damage to electronic devices. Typical commercial-off-the-shelf (COTS) components are not able withstand such an environment, and any electronics operating in these extreme conditions must be designed to accommodate such operation. This dissertation describes the development of a high-speed, high-resolution, multi-modulus prescaler capable of operating in an extreme environment. This prescaler has been developed using current-mode logic (CML) on a 180-nm silicon-germanium (SiGe) BiCMOS process. The prescaler is capable of operating up to at least 5.4 GHz over a division range of 16-48 with a total of 27 configurable moduli. The prescaler is designed to provide excellent ionizing radiation hardness, single-event latch-up (SEL) immunity, and single-event upset (SEU) resistance over a temperature range of −180°C to 125°C

Energy-efficient wireline transceivers

Power-efficient wireline transceivers are highly demanded by many applications in high performance computation and communication systems. Apart from transferring a wide range of data rates to satisfy the interconnect bandwidth requirement, the transceivers have very tight power budget and are expected to be fully integrated. This thesis explores enabling techniques to implement such transceivers in both circuit and system levels. Specifically, three prototypes will be presented: (1) a 5Gb/s reference-less clock and data recovery circuit (CDR) using phase-rotating phase-locked loop (PRPLL) to conduct phase control so as to break several fundamental trade-offs in conventional receivers; (2) a 4-10.5Gb/s continuous-rate CDR with novel frequency acquisition scheme based on bang-bang phase detector (BBPD) and a ring oscillator-based fractional-N PLL as the low noise wide range DCO in the CDR loop; (3) a source-synchronous energy-proportional link with dynamic voltage and frequency scaling (DVFS) and rapid on/off (ROO) techniques to cut the link power wastage at system level. The receiver/transceiver architectures are highly digital and address the requirements of new receiver architecture development, wide operating range, and low power/area consumption while being fully integrated. Experimental results obtained from the prototypes attest the effectiveness of the proposed techniques

Scalable Array Transceivers with Wide Frequency Tuning Range for Next Generation Radios

Scalable array transceivers with wide frequency tuning range are attractive for next-generationradios. Key challenges for such radios include generation of LO signals with widefrequency tuning range, scalable synchronization between multiple array unit cells andtolerance to in-band and out-of-band interferers. This thesis presents approaches toaddress these challenges in commercial CMOS technologies.The first part focuses on a series resonant mode-switching VCO architecture thatachieves both state-of-art area and power efficiency with an octave frequency tuningrange from 6.4-14 GHz achieved 186-dB-188-dB Figure-of-Merit (FoM) in 65 nm CMOStechnology. The scalability of this approach towards achieving even larger FTR is alsodemonstrated by a triple-mode 2.2 GHz to 8.7 GHz (119% FTR) CMOS VCO.In the second part a scalable, single-wire coupled-PLL architecture for RF mm-wavearrays is presented. The proposed architecture preserves the simplicity of a daisy-chained LO distribution, compensates for phase offset due to interconnect, and provides phasenoise improvement commensurate to the number of coupled PLLs. Measurements on a28 GHz CMOS prototype demonstrate the feasibility of this scheme.The third part of this thesis presents filtering techniques for in-band blocker suppression.A spatial spectral notch filter design for MIMO digital beam forming arrays is proposedto relax the ADC dynamic range requirement. Orthogonal properties of Walsh functionsincorporated into passive N-path approach enables reconfigurable notches at multiplefrequencies and angles-of-incidence. A 0.3 GHz-1.4 GHz four-element array prototypeimplemented in 65 nm CMOS achieves > 15-dB notch filtering at RF input for twoblockers while causing < 3-dB NF degradation.Finally, a code-domain N-path receiver (RX) is proposed based on pseudo-random(PN) code-modulated LO pulses for simultaneous transmission and reception (STAR)applications. A combination of Walsh-Function and PN sequence is proposed to createcode-domain matched filter at the RF frontend which reflects unknown in-band blockersand rejects known in-band TX self-interference (SI) by using orthogonal codes at RXinput thereby maximizing the SNR of the received signals. The resulting prototype in65 nm is functional from 0.3 GHz-1.4 GHz with 35 dB gain and concurrently receivestwo code-modulated signals. Proposed transmitter (TX) SI mitigation approach resultsin 38.5 dB rejection for -11.8 dBm 1.46 Mb s QPSK modulated SI at RX input. TheRX achieves 23.7 dBm OP1dB for in-band SI, while consuming ∼35 mW and occupies0.31 mm2Keywords: Passive Mixers, dual band, TX self-Interferer, synchronisation, STAR, Code domain N-path receiver, mode switching, notch filter, Phase locked loops, Octave tuning range, CMOS, phase noise, VCO, large-scale 5G mm-wave arrays, resonator, Simultaneous transmit and receive, resonator band-switching, LO distribution, scalable coupled-PLL, N-path passive mixers, MIMO arrays, digital beamforming, CDMA, phased arrays, wide tuning range, Walsh Functio

Development and Test of a High Performance Multi Channel Readout System on a Chip with Application in PET/MR

The availability of new, compact, magnetic field tolerant sensors suitable for PET has opened the opportunity to build highly integrated PET scanners that can be included in commercial MR scanners. This combination has long been expected to have big advantages over existing systems combining PET and CT. This thesis describes my work towards building a highly integrated readout ASIC for application in PET/MR within the framework of the HYPERImage and SUBLIMA projects. It also gives a brief introduction into both PET and MR to understand the unique challenges for the readout system caused by each system, and their combination. A number of typical solutions for different requirements of the ASIC - timing measurements, trigger generation, and energy readout - and contemporary readout systems are presented to put our system in context. Detailed measurements have been performed to evaluate the performance of the ASIC, and the setup and results are presented here

Voyager spacecraft phase B, task D. Volume 7 - Preliminary OSE and MDE Final report

Systems analysis and preliminary requirements for mission dependent and operational support equipment for Voyager Mars spacecraf