Power frequency interference and suppression in measurement of power transmission tower grounding resistance

“If you want peace, work for justice.” – Pope Paul VI This paper explores how the children’s right to be heard is implemented in the criminal proceedings in Romania and Norway. The judicial practices in the two countries are analysed in relation to four elements identified in the literature as relevant to the child’s right to be heard- space, voice, audience and influence. The two juvenile justice systems are then compared to each other, as well as to international best practices, with the final aim of identifying small-scale measures worth disseminating in Romania and Norway to strengthen the effectiveness of child’s right to be heard. The paper argues that a more effective implementation of the children’s right to be heard strengthen all the array of the children’s rights, makes the juvenile justice system more child-friendly and facilitates the transition from conflict and punitive justice towards positive peace. Keywords: right of the child to be heard, juvenile justice, children’s rights, child-friendly justic

New Aspects of Fault Diagnosis of Nonlinear Analog Circuits

The paper is focused on nonlinear analog circuits, with the special attention paid to circuits comprising bipolar and MOS transistors manufactured in micrometer and submicrometer technology. The problem of fault diagnosis of this class of circuits is discussed, including locating faulty elements and evaluating their parameters. The paper deals with multiple parametric fault diagnosis using the simulation after test approach as well as detection and location of single catastrophic faults, using the simulation before test approach. The discussed methods are based on diagnostic test, leading to a system of nonlinear algebraic type equations, which are not given in explicit analytical form. An important and new aspect of the fault diagnosis is finding multiple solutions of the test equation, i.e. several sets of the parameters values that meet the test. Another new problems in this area are global fault diagnosis of technological parameters in CMOS circuits fabricated in submicrometer technology and testing the circuits  having multiple DC operating points. To solve these problems several methods have been recently developed, which employ  different concepts and mathematical tools of nonlinear analysis. In this paper they are sketched and illustrated.  All the discussed methods are based on the homotopy (continuation) idea. It is shown that various versions of homotopy and combinations  of the homotopy with some other mathematical algorithms lead to very powerful tools for fault diagnosis of nonlinear analog circuits.  To trace the homotopy path which allows finding multiple solutions, the simplicial method, the restart method, the theory of linear complementarity problem and Lemke's algorithm are employed. For illustration four numerical examples are given

Fault diagnostic instrumentation design for environmental control and life support systems

As a development phase moves toward flight hardware, the system availability becomes an important design aspect which requires high reliability and maintainability. As part of continous development efforts, a program to evaluate, design, and demonstrate advanced instrumentation fault diagnostics was successfully completed. Fault tolerance designs for reliability and other instrumenation capabilities to increase maintainability were evaluated and studied

Sustainable Fault-handling Of Reconfigurable Logic Using Throughput-driven Assessment

A sustainable Evolvable Hardware (EH) system is developed for SRAM-based reconfigurable Field Programmable Gate Arrays (FPGAs) using outlier detection and group testing-based assessment principles. The fault diagnosis methods presented herein leverage throughput-driven, relative fitness assessment to maintain resource viability autonomously. Group testing-based techniques are developed for adaptive input-driven fault isolation in FPGAs, without the need for exhaustive testing or coding-based evaluation. The techniques maintain the device operational, and when possible generate validated outputs throughout the repair process. Adaptive fault isolation methods based on discrepancy-enabled pair-wise comparisons are developed. By observing the discrepancy characteristics of multiple Concurrent Error Detection (CED) configurations, a method for robust detection of faults is developed based on pairwise parallel evaluation using Discrepancy Mirror logic. The results from the analytical FPGA model are demonstrated via a self-healing, self-organizing evolvable hardware system. Reconfigurability of the SRAM-based FPGA is leveraged to identify logic resource faults which are successively excluded by group testing using alternate device configurations. This simplifies the system architect\u27s role to definition of functionality using a high-level Hardware Description Language (HDL) and system-level performance versus availability operating point. System availability, throughput, and mean time to isolate faults are monitored and maintained using an Observer-Controller model. Results are demonstrated using a Data Encryption Standard (DES) core that occupies approximately 305 FPGA slices on a Xilinx Virtex-II Pro FPGA. With a single simulated stuck-at-fault, the system identifies a completely validated replacement configuration within three to five positive tests. The approach demonstrates a readily-implemented yet robust organic hardware application framework featuring a high degree of autonomous self-control

Test Strategies for Embedded ADC Cores in a System-on-Chip, A Case Study

Testing of a deeply embedded mixed-signal core in a System-on-Chip (SoC) is a challenging issue due to the communication bottleneck in accessing the core from external automatic test equipment. Consequently, in many cases the preferred approach is built-in self-test (BIST), where the major part of test activity is performed within the unit-under-test and only final results are communicated to the external tester. IEEE Standard 1500 provides efficient test infrastructure for testing digital cores; however, its applications in mixed-signal core test remain an open issue. In this paper we address the problem of implementing BIST of a mixed-signal core in a IEEE Std 1500 test wrapper and discuss advantages and drawbacks of different test strategies. While the case study is focused on histogram based test of ADC, test strategies of other types of mixed-signal cores related to trade-off between performance (i.e., test time) and required resources are likely to follow similar conclusions

Measurement of fault latency in a digital avionic miniprocessor

The results of fault injection experiments utilizing a gate-level emulation of the central processor unit of the Bendix BDX-930 digital computer are presented. The failure detection coverage of comparison-monitoring and a typical avionics CPU self-test program was determined. The specific tasks and experiments included: (1) inject randomly selected gate-level and pin-level faults and emulate six software programs using comparison-monitoring to detect the faults; (2) based upon the derived empirical data develop and validate a model of fault latency that will forecast a software program's detecting ability; (3) given a typical avionics self-test program, inject randomly selected faults at both the gate-level and pin-level and determine the proportion of faults detected; (4) determine why faults were undetected; (5) recommend how the emulation can be extended to multiprocessor systems such as SIFT; and (6) determine the proportion of faults detected by a uniprocessor BIT (built-in-test) irrespective of self-test

Fault tolerant data management system

Described in detail are: (1) results obtained in modifying the onboard data management system software to a multiprocessor fault tolerant system; (2) a functional description of the prototype buffer I/O units; (3) description of modification to the ACADC and stimuli generating unit of the DTS; and (4) summaries and conclusions on techniques implemented in the rack and prototype buffers. Also documented is the work done in investigating techniques of high speed (5 Mbps) digital data transmission in the data bus environment. The application considered is a multiport data bus operating with the following constraints: no preferred stations; random bus access by all stations; all stations equally likely to source or sink data; no limit to the number of stations along the bus; no branching of the bus; and no restriction on station placement along the bus

Low-Computational-Cost Hybrid FEM-Analytical Induction Machine Model for the Diagnosis of Rotor Eccentricity, Based on Sparse Identification Techniques and Trigonometric Interpolation

[EN] Since it is not efficient to physically study many machine failures, models of faulty induction machines (IMs) have attracted a rising interest. These models must be accurate enough to include fault effects and must be computed with relatively low resources to reproduce different fault scenarios. Moreover, they should run in real time to develop online condition-monitoring (CM) systems. Hybrid finite element method (FEM)-analytical models have been recently proposed for fault diagnosis purposes since they keep good accuracy, which is widely accepted, and they can run in real-time simulators. However, these models still require the full simulation of the FEM model to compute the parameters of the analytical model for each faulty scenario with its corresponding computing needs. To address these drawbacks (large computing power and memory resources requirements) this paper proposes sparse identification techniques in combination with the trigonometric interpolation polynomial for the computation of IM model parameters. The proposed model keeps accuracy similar to a FEM model at a much lower computational effort, which could contribute to the development and to the testing of condition-monitoring systems. This approach has been applied to develop an IM model under static eccentricity conditions, but this may extend to other fault types.This work was supported by the Spanish "Ministerio de Ciencia, Innovacion y Universidades (MCIU)", the "Agencia Estatal de Investigacion (AEI)" and the "Fondo Europeo de Desarrollo Regional (FEDER)" in the framework of the "Proyectos I+D+i -Retos Investigacion 2018", project reference RTI2018-102175-B-I00 (MCIU/AEI/FEDER, UE).Terrón-Santiago, C.; Martinez-Roman, J.; Puche-Panadero, R.; Sapena-Bano, A. (2021). Low-Computational-Cost Hybrid FEM-Analytical Induction Machine Model for the Diagnosis of Rotor Eccentricity, Based on Sparse Identification Techniques and Trigonometric Interpolation. Sensors. 21(21):6963-6987. https://doi.org/10.3390/s21216963S69636987212