Testing mixed-signal cores: a practical oscillation-based test in an analog macrocell

A formal set of design decisions can aid in using oscillation-based test (OBT) for analog subsystems in SoCs. The goal is to offer designers testing options that do not have significant area overhead, performance degradation, or test time. This work shows that OBT is a potential candidate for IP providers to use in combination with functional test techniques. We have shown how to modify the basic concept of OBT to come up with a practical method. Using our approach, designers can use OBT to pave the way for future developments in SoC testing, and it is simple to extend this idea to BIST.European Union 2635

IEEE Standard 1500 Compliance Verification for Embedded Cores

Core-based design and reuse are the two key elements for an efficient system-on-chip (SoC) development. Unfortunately, they also introduce new challenges in SoC testing, such as core test reuse and the need of a common test infrastructure working with cores originating from different vendors. The IEEE 1500 Standard for Embedded Core Testing addresses these issues by proposing a flexible hardware test wrapper architecture for embedded cores, together with a core test language (CTL) used to describe the implemented wrapper functionalities. Several intellectual property providers have already announced IEEE Standard 1500 compliance in both existing and future design blocks. In this paper, we address the problem of guaranteeing the compliance of a wrapper architecture and its CTL description to the IEEE Standard 1500. This step is mandatory to fully trust the wrapper functionalities in applying the test sequences to the core. We present a systematic methodology to build a verification framework for IEEE Standard 1500 compliant cores, allowing core providers and/or integrators to verify the compliance of their products (sold or purchased) to the standar

VLSI Revisited - Revival in Japan

This paper describes the abundance of semiconductor consortia that have come into existence in Japan since the mid-1990s. They clearly reflect the ambition of the government - through its reorganized ministry METI and company initiatives - to regain some of the industrial and technological leadership that Japan has lost. The consortia landscape is very different in Japan compared with EU and the US. Outside Japan the universities play a much bigger and very important role. In Europe there has emerged close collaboration, among national government agencies, companies and the EU Commission in supporting the IT sector with considerable attention to semiconductor technologies. Another major difference, and possibly the most important one, is the fact that US and EU consortia include and mix partners from different areas of the semiconductor landscape including wafer makers, material suppliers, equipment producers and integrated device makers.semiconductors, Hitachi, Sony, Toshiba, Elpida, Renesas, Sematech, VLSI, JESSI, MEDEA, ASPLA, MIRAI, innovation system

Programmable photonics : an opportunity for an accessible large-volume PIC ecosystem

We look at the opportunities presented by the new concepts of generic programmable photonic integrated circuits (PIC) to deploy photonics on a larger scale. Programmable PICs consist of waveguide meshes of tunable couplers and phase shifters that can be reconfigured in software to define diverse functions and arbitrary connectivity between the input and output ports. Off-the-shelf programmable PICs can dramatically shorten the development time and deployment costs of new photonic products, as they bypass the design-fabrication cycle of a custom PIC. These chips, which actually consist of an entire technology stack of photonics, electronics packaging and software, can potentially be manufactured cheaper and in larger volumes than application-specific PICs. We look into the technology requirements of these generic programmable PICs and discuss the economy of scale. Finally, we make a qualitative analysis of the possible application spaces where generic programmable PICs can play an enabling role, especially to companies who do not have an in-depth background in PIC technology

VLSI REVISITED – REVIVAL IN JAPAN

This paper describes the abundance of semiconductor consortia that have come into existence in Japan since the mid-1990s. They clearly reflect the ambition of the government – through its reorganized ministry METI and company initiatives - to regain some of the industrial and technological leadership that Japan has lost. The consortia landscape is very different in Japan compared with EU and the US. Outside Japan the universities play a much bigger and very important role. In Europe there has emerged close collaboration, among national government agencies, companies and the EU Commission in supporting the IT sector with considerable attention to semiconductor technologies. Another major difference, and possibly the most important one, is the fact that US and EU consortia include and mix partners from different areas of the semiconductor landscape including wafer makers, material suppliers, equipment producers and integrated device makers.semiconductors; Hitachi; Sony; Toshiba; Elpida; Renesas; Sematech; VLSI; JESSI; MEDEA; ASPLA; MIRAI; innovation system

Printed Circuit Board (PCB) design process and fabrication

This module describes main characteristics of Printed Circuit Boards (PCBs). A brief history of PCBs is introduced in the first chapter. Then, the design processes and the fabrication of PCBs are addressed and finally a study case is presented in the last chapter of the module.Peer ReviewedPostprint (published version

A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier

Concentric distributed active transformers (DAT) are used to implement a fully-integrated quad-band power amplifier (PA) in a standard 130 nm CMOS process. The DAT enables the power amplifier to integrate the input and output matching networks on the same silicon die. The PA integrates on-chip closed-loop power control and operates under supply voltages from 2.9 V to 5.5 V in a standard micro-lead-frame package. It shows no oscillations, degradation, or failures for over 2000 hours of operation with a supply of 6 V at 135° under a VSWR of 15:1 at all phase angles and has also been tested for more than 2 million device-hours (with ongoing reliability monitoring) without a single failure under nominal operation conditions. It produces up to +35 dBm of RF power with power-added efficiency of 51%

Proceedings of Abstracts Engineering and Computer Science Research Conference 2019

© 2019 The Author(s). This is an open-access work distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited. For further details please see https://creativecommons.org/licenses/by/4.0/. Note: Keynote: Fluorescence visualisation to evaluate effectiveness of personal protective equipment for infection control is © 2019 Crown copyright and so is licensed under the Open Government Licence v3.0. Under this licence users are permitted to copy, publish, distribute and transmit the Information; adapt the Information; exploit the Information commercially and non-commercially for example, by combining it with other Information, or by including it in your own product or application. Where you do any of the above you must acknowledge the source of the Information in your product or application by including or linking to any attribution statement specified by the Information Provider(s) and, where possible, provide a link to this licence: http://www.nationalarchives.gov.uk/doc/open-government-licence/version/3/This book is the record of abstracts submitted and accepted for presentation at the Inaugural Engineering and Computer Science Research Conference held 17th April 2019 at the University of Hertfordshire, Hatfield, UK. This conference is a local event aiming at bringing together the research students, staff and eminent external guests to celebrate Engineering and Computer Science Research at the University of Hertfordshire. The ECS Research Conference aims to showcase the broad landscape of research taking place in the School of Engineering and Computer Science. The 2019 conference was articulated around three topical cross-disciplinary themes: Make and Preserve the Future; Connect the People and Cities; and Protect and Care

Integrated Circuit Design in US High-Energy Physics

This whitepaper summarizes the status, plans, and challenges in the area of integrated circuit design in the United States for future High Energy Physics (HEP) experiments. It has been submitted to CPAD (Coordinating Panel for Advanced Detectors) and the HEP Community Summer Study 2013(Snowmass on the Mississippi) held in Minnesota July 29 to August 6, 2013. A workshop titled: US Workshop on IC Design for High Energy Physics, HEPIC2013 was held May 30 to June 1, 2013 at Lawrence Berkeley National Laboratory (LBNL). A draft of the whitepaper was distributed to the attendees before the workshop, the content was discussed at the meeting, and this document is the resulting final product. The scope of the whitepaper includes the following topics: Needs for IC technologies to enable future experiments in the three HEP frontiers Energy, Cosmic and Intensity Frontiers; Challenges in the different technology and circuit design areas and the related R&D needs; Motivation for using different fabrication technologies; Outlook of future technologies including 2.5D and 3D; Survey of ICs used in current experiments and ICs targeted for approved or proposed experiments; IC design at US institutes and recommendations for collaboration in the future