The future of computing beyond Moore's Law.

Moore's Law is a techno-economic model that has enabled the information technology industry to double the performance and functionality of digital electronics roughly every 2 years within a fixed cost, power and area. Advances in silicon lithography have enabled this exponential miniaturization of electronics, but, as transistors reach atomic scale and fabrication costs continue to rise, the classical technological driver that has underpinned Moore's Law for 50 years is failing and is anticipated to flatten by 2025. This article provides an updated view of what a post-exascale system will look like and the challenges ahead, based on our most recent understanding of technology roadmaps. It also discusses the tapering of historical improvements, and how it affects options available to continue scaling of successors to the first exascale machine. Lastly, this article covers the many different opportunities and strategies available to continue computing performance improvements in the absence of historical technology drivers. This article is part of a discussion meeting issue 'Numerical algorithms for high-performance computational science'

SSIVP: Spacecraft Supercomputing Experiment for STP-H6

The Department of Defense Space Test Program (STP) provides spaceflight opportunities for conducting on-orbit research and technology demonstrations to advance the future of spacecraft. STP-H6, the next mission of the program to the International Space Station (ISS), will include a prototype spacecraft supercomputing experiment and framework, called Spacecraft Supercomputing for Image and Video Processing (SSIVP), developed at the National Science Foundation (NSF) Center for High-Performance Reconfigurable Computing (CHREC) at the University of Pittsburgh. SSIVP introduces scalable, high-performance computing (HPC) principles to a CubeSat form-factor to advance the state of the art in space computing. SSIVP adopts the CHREC Space Processor (CSP) concept, a multifaceted design philosophy for a hybrid system of commercial and radiation-hardened (rad-hard) components supplemented with fault-tolerant computing, and a hybrid processor combining fixed-logic CPU and reconfigurable-logic FPGA. SSIVP features five flight-qualified CSPv1 computers as compute nodes, to facilitate this supercomputing concept, and one μCSP smart module, for running a Gallium Nitride (GaN)-based power converter sub-experiment. SSIVP is a versatile, heterogenous platform capable of processing application workloads in the processor or on runtime-reconfigurable FPGA accelerators. In this paper, we present the flight hardware and software, frameworks for parallel and dependable computing, and mission objectives for SSIVP

Survey and Analysis of Production Distributed Computing Infrastructures

This report has two objectives. First, we describe a set of the production distributed infrastructures currently available, so that the reader has a basic understanding of them. This includes explaining why each infrastructure was created and made available and how it has succeeded and failed. The set is not complete, but we believe it is representative. Second, we describe the infrastructures in terms of their use, which is a combination of how they were designed to be used and how users have found ways to use them. Applications are often designed and created with specific infrastructures in mind, with both an appreciation of the existing capabilities provided by those infrastructures and an anticipation of their future capabilities. Here, the infrastructures we discuss were often designed and created with specific applications in mind, or at least specific types of applications. The reader should understand how the interplay between the infrastructure providers and the users leads to such usages, which we call usage modalities. These usage modalities are really abstractions that exist between the infrastructures and the applications; they influence the infrastructures by representing the applications, and they influence the ap- plications by representing the infrastructures

Embedded Linux as a Platform for Dynamically Self-Reconfiguring Systems-On-Chip

We have previously argued the benefits of embedded Linux as an operating system platform for reconfigurable system-on-chip design. In this paper we describe our approach to building tools for the implementation of dynamically and self-reconfigurable systems, and show that embedded Linux is a natural and powerful platform on which to build these tools. We present examples and demonstrations that show how complex operations such as obtaining partial bit streams from remote servers and initiating reconfiguration are achieved with a single line of Linux shell script

Autonomous Recovery Of Reconfigurable Logic Devices Using Priority Escalation Of Slack

Field Programmable Gate Array (FPGA) devices offer a suitable platform for survivable hardware architectures in mission-critical systems. In this dissertation, active dynamic redundancy-based fault-handling techniques are proposed which exploit the dynamic partial reconfiguration capability of SRAM-based FPGAs. Self-adaptation is realized by employing reconfiguration in detection, diagnosis, and recovery phases. To extend these concepts to semiconductor aging and process variation in the deep submicron era, resilient adaptable processing systems are sought to maintain quality and throughput requirements despite the vulnerabilities of the underlying computational devices. A new approach to autonomous fault-handling which addresses these goals is developed using only a uniplex hardware arrangement. It operates by observing a health metric to achieve Fault Demotion using Recon- figurable Slack (FaDReS). Here an autonomous fault isolation scheme is employed which neither requires test vectors nor suspends the computational throughput, but instead observes the value of a health metric based on runtime input. The deterministic flow of the fault isolation scheme guarantees success in a bounded number of reconfigurations of the FPGA fabric. FaDReS is then extended to the Priority Using Resource Escalation (PURE) online redundancy scheme which considers fault-isolation latency and throughput trade-offs under a dynamic spare arrangement. While deep-submicron designs introduce new challenges, use of adaptive techniques are seen to provide several promising avenues for improving resilience. The scheme developed is demonstrated by hardware design of various signal processing circuits and their implementation on a Xilinx Virtex-4 FPGA device. These include a Discrete Cosine Transform (DCT) core, Motion Estimation (ME) engine, Finite Impulse Response (FIR) Filter, Support Vector Machine (SVM), and Advanced Encryption Standard (AES) blocks in addition to MCNC benchmark circuits. A iii significant reduction in power consumption is achieved ranging from 83% for low motion-activity scenes to 12.5% for high motion activity video scenes in a novel ME engine configuration. For a typical benchmark video sequence, PURE is shown to maintain a PSNR baseline near 32dB. The diagnosability, reconfiguration latency, and resource overhead of each approach is analyzed. Compared to previous alternatives, PURE maintains a PSNR within a difference of 4.02dB to 6.67dB from the fault-free baseline by escalating healthy resources to higher-priority signal processing functions. The results indicate the benefits of priority-aware resiliency over conventional redundancy approaches in terms of fault-recovery, power consumption, and resource-area requirements. Together, these provide a broad range of strategies to achieve autonomous recovery of reconfigurable logic devices under a variety of constraints, operating conditions, and optimization criteria

STP-H7-CASPR: A Transition from Mission Concept to Launch

The Configurable and Autonomous Sensor Processing Research (CASPR) project is a university-led experiment developed by student and faculty researchers at the NSF Center for Space, High-performance, and Resilient Computing (SHREC) at the University of Pittsburgh for the Space Test Program – Houston 7 (STP-H7) mission to the International Space Station (ISS). Autonomous sensor processing, the mission theme of the CASPR experiment, is enabled by combining novel sensor technologies with innovative computing techniques on resilient and high-performance flight hardware in a small satellite (SmallSat) form-factor. CASPR includes the iSIM-90, an innovative, high-resolution optical payload for Earth-observation missions developed by SATLANTIS MICROSATS SL. For the CASPR mission, the opto-mechanics of iSIM-90 will be mounted atop a gimbal-actuated platform for agile, low-GRD (ground-resolved distance), and multispectral Earth-observation imaging. This mission will also feature the Prophesee Sisley neuromorphic, event-driven sensor for space situational awareness applications. The CASPR avionics system consists of the following: three radiation-tolerant, reconfigurable space computers, including one flight-proven CSP and two next-gen SSPs; one μCSP Smart Module; one power card; and one backplane. CASPR also features a sub-experiment with an AMD GPU to evaluate new accelerator technologies for space. CASPR is a highly versatile experiment combining a variety of compute and sensor technologies to demonstrate on-orbit capabilities in onboard data analysis, mission operations, and spacecraft autonomy. As a research sandbox, CASPR enables new software and hardware to be remotely uploaded to further enhance mission capabilities. Finally, as a university-led mission, cost is a limiting constraint, leading to budget-driven design decisions and the use of affordable methods and procedures. Other factors, such as a power budget and limited equipment, facilities, and engineering resources, pose additional challenges to the CASPR mission. To address these challenges, we describe cost-effective procedures and methods used in the assembly, integration, and testing of the CASPR experiment

MIMO Evolution Beyond 5G Through Reconfigurable Intelligent Surfaces and Fluid Antenna Systems

With massive deployment, multiple-input-multiple-output (MIMO) systems continue to take mobile communications to new heights, but the ever-increasing demands mean that there is a need to look beyond MIMO and pursue the next disruptive wireless technologies. Reconfigurable intelligent surface (RIS) is widely considered a key candidate technology block to provide the next generational leap. The first part of this article provides an updated overview of the conventional reflection-based RIS technology, which complements the existing literature to include active and semiactive RIS, and the synergies with cell-free massive MIMO (CF mMIMO). Then, we widen the scope to discuss the surface-wave-assisted RIS that represents a different design dimension in utilizing metasurface technologies. This goes beyond being a passive reflector and can use the surface as an intelligent propagation medium for superb radio propagation efficiency. The third part of this article turns the attention to the fluid antenna, a novel antenna technology that enables a diverse form of reconfigurability that can combine with RIS for ultrahigh capacity, power efficiency, and scalability. This article concludes with a discussion of the potential synergies that can be exploited between MIMO, RIS, and fluid antennas