A Real-Time ANPC Inverter Digital Twin with Integrated Design-For-Trust

The demand for renewable energy has increased over the last few years, and so has the demand for greater expectations within the energy market. This increasing trend has been accompanied by more significant usage of internet-connected devices (IoT), leading to critical electrical infrastructure being connected to the internet. Implementing internet connectivity with such devices and systems provides benefits such as improving the system\u27s performance, facilitating irregularity and anomaly mitigation, and providing additional situational awareness for enhanced decision-making. However, enhancing the connected system with IoT introduces a drawback – a greater vulnerability to cyber-attacks. Cyber-attacks targeting critical infrastructure in the electrical sector have occurred in the United States and Ukraine. These cyber-attacks highlight and expose vulnerabilities that a system inherits when connecting to the internet. These attacks left thousands of customers without electricity for hours until operators could regain control of the electric utility grid. Therefore, to address the vulnerabilities of an internet-connected power electronic device, this work focused on the hardware layer of the system. Implementing a cyber-control system inside the hardware layer can significantly reduce the possibility of an attacker patching malicious controller firmware into a photovoltaic grid-connected inverter, thus mitigating the likelihood that the inverter becomes inactive a cyber-attack scenario. With this mitigation technique, if a cyberattack is successful and an attacker gains control of the network, a cyber-defense technique is in place to mitigate the impact of the cyber-attack. This additional protection layer was developed based on an innovative concept known as Digital Twin (DT). A DT, in this case, replicates an Active-Neutral Point Clamped (ANPC) inverter and was designed using a hardware language known as VHDL (Very High-SpeedIntegrated Circuit Hardware Description Language) and applied to Field-Programmable-GateArray (FPGA). The DT is embedded within the FPGA and contained in a controller board, the UCB (Unified Controller Board), developed by the University of Arkansas electrical engineering team. This UCB also contains two Digital Signal Processors (DSPs) responsible for generating associated signals to control an authentic physical inverter. These DSP signals are received and processed by the FPGA that implements the DT of an ANPC; in other words, it simulates in realtime the expected output of an actual ANPC inverter using the signals from the DSP. When a new firmware is ready to be patched, the DT provides output signals simulating behavior that a real ANPC inverter would generate with the new firmware. The new firmware is tested to check if it meets all the operational requirements established using a Design-For-Trust technique (DFTr). If the new firmware fails in at least one of the DFT tests, it is considered malicious and must be rejected. This work is divided into sections, such as Background, which explains the pieces that were used and the strategy behind this work; Process and Procedure, which explains the methodology that was adopted to prove the reliability and effectiveness of this work; Results and Discussion, where the simulations and results are described and explained; followed by Conclusion and Future work section, which concludes this work and adds possible future projects to continue this work furthe

A Real-Time ANPC Inverter Digital Twin with Integrated Design-For-Trust

The demand for renewable energy has increased over the last few years, and so has the demand for greater expectations within the energy market. This increasing trend has been accompanied by more significant usage of internet-connected devices (IoT), leading to critical electrical infrastructure being connected to the internet. Implementing internet connectivity with such devices and systems provides benefits such as improving the system\u27s performance, facilitating irregularity and anomaly mitigation, and providing additional situational awareness for enhanced decision-making. However, enhancing the connected system with IoT introduces a drawback – a greater vulnerability to cyber-attacks. Cyber-attacks targeting critical infrastructure in the electrical sector have occurred in the United States and Ukraine. These cyber-attacks highlight and expose vulnerabilities that a system inherits when connecting to the internet. These attacks left thousands of customers without electricity for hours until operators could regain control of the electric utility grid. Therefore, to address the vulnerabilities of an internet-connected power electronic device, this work focused on the hardware layer of the system. Implementing a cyber-control system inside the hardware layer can significantly reduce the possibility of an attacker patching malicious controller firmware into a photovoltaic grid-connected inverter, thus mitigating the likelihood that the inverter becomes inactive a cyber-attack scenario. With this mitigation technique, if a cyberattack is successful and an attacker gains control of the network, a cyber-defense technique is in place to mitigate the impact of the cyber-attack. This additional protection layer was developed based on an innovative concept known as Digital Twin (DT). A DT, in this case, replicates an Active-Neutral Point Clamped (ANPC) inverter and was designed using a hardware language known as VHDL (Very High-SpeedIntegrated Circuit Hardware Description Language) and applied to Field-Programmable-GateArray (FPGA). The DT is embedded within the FPGA and contained in a controller board, the UCB (Unified Controller Board), developed by the University of Arkansas electrical engineering team. This UCB also contains two Digital Signal Processors (DSPs) responsible for generating associated signals to control an authentic physical inverter. These DSP signals are received and processed by the FPGA that implements the DT of an ANPC; in other words, it simulates in realtime the expected output of an actual ANPC inverter using the signals from the DSP. When a new firmware is ready to be patched, the DT provides output signals simulating behavior that a real ANPC inverter would generate with the new firmware. The new firmware is tested to check if it meets all the operational requirements established using a Design-For-Trust technique (DFTr). If the new firmware fails in at least one of the DFT tests, it is considered malicious and must be rejected. This work is divided into sections, such as Background, which explains the pieces that were used and the strategy behind this work; Process and Procedure, which explains the methodology that was adopted to prove the reliability and effectiveness of this work; Results and Discussion, where the simulations and results are described and explained; followed by Conclusion and Future work section, which concludes this work and adds possible future projects to continue this work furthe

Remote control and monitoring of power systems

Includes synopsis.Includes bibliographical references (leaves 87-93).Power systems are typically complex and can be affected by their environment in ways that cannot be completely predicted by their designers. It is thus imperative that monitoring is considered as part of the design of new power systems. Due to the associated costs of maintenance, repair, and downtime, monitoring these systems is particularly important when the installations are remote. Remote locations benefit greatly from renewable energy sources. As a result, this work focuses on a novel Hybrid Inverter system developed by Optimal Power Solutions Pty. Ltd. (OPS). This system uses renewable energy sources, grid power, and diesel generators together with a bi-directional inverter to supply a remote location with grid-quality power

Space station automation of common module power management and distribution

The purpose is to automate a breadboard level Power Management and Distribution (PMAD) system which possesses many functional characteristics of a specified Space Station power system. The automation system was built upon 20 kHz ac source with redundancy of the power buses. There are two power distribution control units which furnish power to six load centers which in turn enable load circuits based upon a system generated schedule. The progress in building this specified autonomous system is described. Automation of Space Station Module PMAD was accomplished by segmenting the complete task in the following four independent tasks: (1) develop a detailed approach for PMAD automation; (2) define the software and hardware elements of automation; (3) develop the automation system for the PMAD breadboard; and (4) select an appropriate host processing environment

Advanced Process Monitoring for Industry 4.0

This book reports recent advances on Process Monitoring (PM) to cope with the many challenges raised by the new production systems, sensors and “extreme data” conditions that emerged with Industry 4.0. Concepts such as digital-twins and deep learning are brought to the PM arena, pushing forward the capabilities of existing methodologies to handle more complex scenarios. The evolution of classical paradigms such as Latent Variable modeling, Six Sigma and FMEA are also covered. Applications span a wide range of domains such as microelectronics, semiconductors, chemicals, materials, agriculture, as well as the monitoring of rotating equipment, combustion systems and membrane separation processes

LANGUAGE LEARNING STRATEGIES OF EFL STUDENTS AT SMAN 5 PAYAKUMBUH

Mhd Rasid Hamdi (2022) : Strategi pembelajaran bahasa siswa EFL di SMAN 5 Payakumbuh Penelitian ini berfokus pada mengidentifikasi strategi pembelajaran bahasa yang paling sering digunakan oleh siswa EFL. Penelitian ini merupakan penelitian dengan desain metode campuran sekuensial eksplanatori. Strategi pembelajaran merupakan salah satu faktor utama yang dapat membantu menentukan bagaimana siswa belajar. Dengan mengetahui dan memahami strategi pembelajaran bahasa yang digunakan siswa dalam proses pembelajaran. Proses pembelajaran akan menjadi lebih baik. Namun, siswa memiliki kepribadian yang berbeda, sehingga mereka belajar dalam berbagai strategi yang berbeda. Pengumpulan data dilakukan melalui kuesioner dan wawancara. Kuesioner dan wawancara digunakan untuk mengetahui strategi pembelajaran apa yang digunakan oleh siswa. Wawancara berfungsi untuk memvalidasi data dari kuesioner. Kuesioner sebagai instrumen pengumpulan data yang diadopsi dari Strategy Inventory for Language Learning (SILL) oleh Oxford (1989) dibagikan kepada 20 siswa kelas X dan 20 siswa kelas XI SMAN 5 Payakumbuh untuk mengamati strategi pembelajaran bahasa mereka. Data tersebut diolah dan dianalisis melalui Jeffrey's Amazing Statistics Program (JASP). Data yang dikumpulkan dari pertanyaan wawancara dianalisis secara kualitatif. Hasil angket dan wawancara menggambarkan bahwa siswa kelas X dan XI menggunakan semua strategi pembelajaran, meliputi memori, kognitif, kompensasi, meta kognitif, afektif dan sosial. Analisis statistik dan hasil wawancara menunjukkan bahwa kognitif adalah strategi pembelajaran bahasa yang paling disukai oleh siswa kelas sepuluh dan sebelas. Sedangkan, Kompensasi dan afektif adalah strategi pembelajaran bahasa yang paling jarang digunakan oleh siswa kelas sepuluh dan sebelas. Kata Kunci: Pembelajaran EFL, strategi pembelajaran bahasa, pembelajaran bahasa Inggris, siswa , strategi pembelajara

LANGUAGE LEARNING STRATEGIES OF EFL STUDENTS AT SMAN 5 PAYAKUMBUH

Mhd Rasid Hamdi (2022) : Strategi pembelajaran bahasa siswa EFL di SMAN 5 Payakumbuh Penelitian ini berfokus pada mengidentifikasi strategi pembelajaran bahasa yang paling sering digunakan oleh siswa EFL. Penelitian ini merupakan penelitian dengan desain metode campuran sekuensial eksplanatori. Strategi pembelajaran merupakan salah satu faktor utama yang dapat membantu menentukan bagaimana siswa belajar. Dengan mengetahui dan memahami strategi pembelajaran bahasa yang digunakan siswa dalam proses pembelajaran. Proses pembelajaran akan menjadi lebih baik. Namun, siswa memiliki kepribadian yang berbeda, sehingga mereka belajar dalam berbagai strategi yang berbeda. Pengumpulan data dilakukan melalui kuesioner dan wawancara. Kuesioner dan wawancara digunakan untuk mengetahui strategi pembelajaran apa yang digunakan oleh siswa. Wawancara berfungsi untuk memvalidasi data dari kuesioner. Kuesioner sebagai instrumen pengumpulan data yang diadopsi dari Strategy Inventory for Language Learning (SILL) oleh Oxford (1989) dibagikan kepada 20 siswa kelas X dan 20 siswa kelas XI SMAN 5 Payakumbuh untuk mengamati strategi pembelajaran bahasa mereka. Data tersebut diolah dan dianalisis melalui Jeffrey's Amazing Statistics Program (JASP). Data yang dikumpulkan dari pertanyaan wawancara dianalisis secara kualitatif. Hasil angket dan wawancara menggambarkan bahwa siswa kelas X dan XI menggunakan semua strategi pembelajaran, meliputi memori, kognitif, kompensasi, meta kognitif, afektif dan sosial. Analisis statistik dan hasil wawancara menunjukkan bahwa kognitif adalah strategi pembelajaran bahasa yang paling disukai oleh siswa kelas sepuluh dan sebelas. Sedangkan, Kompensasi dan afektif adalah strategi pembelajaran bahasa yang paling jarang digunakan oleh siswa kelas sepuluh dan sebelas. Kata Kunci: Pembelajaran EFL, strategi pembelajaran bahasa, pembelajaran bahasa Inggris, siswa , strategi pembelajara

Exploring Multi-Level Parallelism For Graph-Based Applications Via Algorithm And System Co-Design

Graph processing is at the heart of many modern applications where graphs are used as the basic data structure to represent the entities of interest and the relationships between them. Improving the performance of graph-based applications, especially using parallelism techniques, has drawn significant interest both in academia and industry. On the one hand, modern CPU architectures are able to provide massive computational power by using sophisticated memory hierarchy and multi-level parallelism, including thread-level parallelism, data-level parallelism, etc. On the other hand, graph processing workloads are notoriously challenging for achieving high performance due to their irregular computation pattern and unpredictable control flow. Therefore, how to accelerate the performance of graph-based applications using parallelism is still an open question. This dissertation focuses on providing high performance for graph-based applications. To take full advantage of multi-level parallelism resources provided by CPUs, this dissertation studies the characteristics of graph-based applications and matches their parallel solutions with the underlying hardware via algorithm and system co-design. This dissertation divides graph-based applications into three categories: typical graph algorithms, sequential graph-based applications, and applications with graph-based solutions. The first category comprises typical graph algorithms with available parallel solutions. This dissertation proposes GraphPhi as a new approach to graph processing on emerging Intel Xeon Phi-like architectures. The second category includes specialized graph applications without nontrivial parallel solutions. This dissertation studies a state-of-the-art 2-hop labeling approach named Pruned Landmark Labeling (PLL). This dissertation proposes Batched Vertex-Centric PLL (BVC-PLL), which breaks PLL\u27s inherent dependencies and parallelizes it in a scalable way. The third category includes applications that rely on graph-based solutions. This dissertation studies the sequential search algorithm for the graph-based indexing methods used for the Approximate Nearest Neighbor Search (ANNS) problem. This dissertation proposes Speed-ANN, a parallel similarity search algorithm that reveals hidden intra-query parallelism to accelerate the search speed while fulfilling the high accuracy requirement. Moreover, this dissertation further explores the optimization opportunities for computational graph-based deep neural network inference running on tiny devices, specifically microcontrollers (MCUs). Altogether, this dissertation studies graph-based applications and improves their performance by providing solutions of multi-level parallelism via algorithm and system co-design to match them with the underlying multi-core CPU architectures