ATMP: An Adaptive Tolerance-based Mixed-criticality Protocol for Multi-core Systems

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted ncomponent of this work in other works.The challenge of mixed-criticality scheduling is to keep tasks of higher criticality running in case of resource shortages caused by faults. Traditionally, mixedcriticality scheduling has focused on methods to handle faults where tasks overrun their optimistic worst-case execution time (WCET) estimate. In this paper we present the Adaptive Tolerance based Mixed-criticality Protocol (ATMP), which generalises the concept of mixed-criticality scheduling to handle also faults of other nature, like failure of cores in a multi-core system. ATMP is an adaptation method triggered by resource shortage at runtime. The first step of ATMP is to re-partition the task to the available cores and the second step is to optimise the utility at each core using the tolerance-based real-time computing model (TRTCM). The evaluation shows that the utility optimisation of ATMP can achieve a smoother degradation of service compared to just abandoning tasks

A low-complexity turbo decoder architecture for energy-efficient wireless sensor networks

Turbo codes have recently been considered for energy-constrained wireless communication applications, since they facilitate a low transmission energy consumption. However, in order to reduce the overall energy consumption, Look-Up- Table-Log-BCJR (LUT-Log-BCJR) architectures having a low processing energy consumption are required. In this paper, we decompose the LUT-Log-BCJR architecture into its most fundamental Add Compare Select (ACS) operations and perform them using a novel low-complexity ACS unit. We demonstrate that our architecture employs an order of magnitude fewer gates than the most recent LUT-Log-BCJR architectures, facilitating a 71% energy consumption reduction. Compared to state-of- the-art Maximum Logarithmic Bahl-Cocke-Jelinek-Raviv (Max- Log-BCJR) implementations, our approach facilitates a 10% reduction in the overall energy consumption at ranges above 58 m

Формалізація адаптивного відображення задач у реконфігурованих обчислювальних системах на ПЛІС

Розроблено математичні моделі адаптивної реконфігурації, що визначають значення критеріїв ефективності реконфігурованих обчислень. Запропоновано новий підхід до скорочення критичного часу виконання паралельних алгоритмів за рахунок видалення непродуктивної складової часу реконфігурації з критичного шляху графу алгоритму. Розроблено та досліджено програмну модель запропонованих засобів адаптивного відображення алгоритму на реконфігуровану обчислювальну структуру на ПЛІС.Formal models of adaptive reconfiguration were developed. It allowed determining the value of the performance criteria of reconfigurable computing system. A new approach of reducing the critical execution time of parallel algorithms was proposed by removing reconfiguration time overheads from the critical path of algorithm`s graph. Program model of proposed means for adaptive tasks mapping on reconfigurable FPGA computing structur

Зменшення накладних видатків реконфігурації в реконфігурованих обчислювальних системах

Запропоновано нові засоби реконфігурації, що дозволяють мінімізувати накладні видатки реконфігурації, забезпечуючи підвищення продуктивності динамічно реконфігурованих обчислювальних систем. Запропонований метод повторного використання апаратних ресурсів функціональних блоків, забезпечує інтенсивне прискорення реконфігурації за рахунок видалення всієї непродуктивної складової часу реконфігурації.Предложены новые средства реконфигурации, которые позволяют минимизировать накладные расходы реконфигурации, обеспечивая повышение производительности динамически реконфигурируемых вычислительных систем. Предложенный метод повторного использования аппаратных ресурсов функциональных блоков обеспечивает интенсивнее ускорение реконфигурации за счет удаления всей непродуктивной составляющей времени реконфигурации.The new means of the reconfiguration is proposed that to minimize overheads reconfiguration and to provide improved performance dynamically reconfigurable systems. The proposed reusing hardware resources method of function blocks provides an intensive acceleration reconfiguration by removing all the overhead part-time reconfiguration

Data-Based Assembly Patterns for Overall Equipment Effectiveness at Semi-Automatic Assembly Lines

In industrial practice, production planning is a key factor for manufacturers and suppliers. The entire planning process spans from the appearance of the customer demand to the fulfillment of the demand. Operational execution is based on pre-planned production processes and operations using properly allocated resources. The accurate planning of assembly operations within production is an extremely complex process in terms of efficiency. Predicting stochastically variable efficiencies is difficult due to the ever-changing manufacturing conditions. This paper defines typical assembly process situations for a semi-automatic assembly line and examines their consequence for the Overall Equipment Effectiveness (OEE). Firstly, a literature review demonstrates the scientific relevance. Secondly, the classification of patterns based on assembly process description parameters is described taking into account the positive and negative effects on the OEE. In addition, the assembly patterns and their characteristics are illustrated through a real automotive example

A Survey of Fault-Tolerance Techniques for Embedded Systems from the Perspective of Power, Energy, and Thermal Issues

The relentless technology scaling has provided a significant increase in processor performance, but on the other hand, it has led to adverse impacts on system reliability. In particular, technology scaling increases the processor susceptibility to radiation-induced transient faults. Moreover, technology scaling with the discontinuation of Dennard scaling increases the power densities, thereby temperatures, on the chip. High temperature, in turn, accelerates transistor aging mechanisms, which may ultimately lead to permanent faults on the chip. To assure a reliable system operation, despite these potential reliability concerns, fault-tolerance techniques have emerged. Specifically, fault-tolerance techniques employ some kind of redundancies to satisfy specific reliability requirements. However, the integration of fault-tolerance techniques into real-time embedded systems complicates preserving timing constraints. As a remedy, many task mapping/scheduling policies have been proposed to consider the integration of fault-tolerance techniques and enforce both timing and reliability guarantees for real-time embedded systems. More advanced techniques aim additionally at minimizing power and energy while at the same time satisfying timing and reliability constraints. Recently, some scheduling techniques have started to tackle a new challenge, which is the temperature increase induced by employing fault-tolerance techniques. These emerging techniques aim at satisfying temperature constraints besides timing and reliability constraints. This paper provides an in-depth survey of the emerging research efforts that exploit fault-tolerance techniques while considering timing, power/energy, and temperature from the real-time embedded systems’ design perspective. In particular, the task mapping/scheduling policies for fault-tolerance real-time embedded systems are reviewed and classified according to their considered goals and constraints. Moreover, the employed fault-tolerance techniques, application models, and hardware models are considered as additional dimensions of the presented classification. Lastly, this survey gives deep insights into the main achievements and shortcomings of the existing approaches and highlights the most promising ones

Modeling Mixed-critical Systems in Real-time BIP

International audienceThe proliferation of multi- and manycores creates an important design problem: the design and verification for mixed-criticality constraints in timing and safety, taking into account the resource sharing and hardware faults. In our work, we aim to contribute towards the solution of these problems by using a formal design language - the real time BIP, to model both hardware and software, functionality and scheduling. In this paper we present the initial experiments of modeling mixed-criticality systems in BIP

Volatile STT-RAM Scratchpad Design and Data Allocation for Low Energy

[Abstract] On-chip power consumption is one of the fundamental challenges of current technology scaling. Cache memories consume a sizable part of this power, particularly due to leakage energy. STT-RAM is one of several new memory technologies that have been proposed in order to improve power while preserving performance. It features high density and low leakage, but at the expense of write energy and performance. This article explores the use of STT-RAM--based scratchpad memories that trade nonvolatility in exchange for faster and less energetically expensive accesses, making them feasible for on-chip implementation in embedded systems. A novel multiretention scratchpad partitioning is proposed, featuring multiple storage spaces with different retention, energy, and performance characteristics. A customized compiler-based allocation algorithm suitable for use with such a scratchpad organization is described. Our experiments indicate that a multiretention STT-RAM scratchpad can provide energy savings of 53% with respect to an iso-area, hardware-managed SRAM cache

The Potential of Silicon Photonic Devices based on Micro-Ring Resonator

Silicon photonic is the theory and application of photonic systems that utilize silicon as an optical medium. The fabrication compatibility with current CMOS processes offer vast development and future improvement of optical devices. By using silicon micro-ring resonator, the requirement of high speed on-chip interconnections can be achieved. This paper gives an overview of the recent research on the potential of silicon photonics based on micro-ring resonato