Dual-Vth Independent-Gate FinFETs for Low Power Logic Circuits

This paper describes the electrode work-function, oxide thickness, gate-source/drain underlap, and silicon thickness optimization required to realize dual-Vth independent-gate FinFETs. Optimum values for these FinFET design parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-Vth FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional CMOS gates, e.g., implementing 12 unique Boolean functions using only four transistors. Circuit designs that balance and improve the performance of the novel gates are described. The gates are designed and calibrated using the University of Florida double-gate model into conventional and enhanced technology libraries. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2GHz, the enhanced library reduces total power and the number of fins by 36% and 37%, respectively, over a conventional library designed using shorted-gate FinFETs in 32 nm technology

Novel dual-threshold voltage FinFETs for circuit design and optimization

A great research effort has been invested on finding alternatives to CMOS that have better process variation and subthreshold leakage. From possible candidates, FinFET is the most compatible with respect to CMOS and it has shown promising leakage and speed performance. This thesis introduces basic characteristics of FinFETs and the effects of FinFET physical parameters on their performance are explained quantitatively. I show how dual- V th independent-gate FinFETs can be fabricated by optimizing their physical parameters. Optimum values for these physical parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-14, FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than CMOS gates. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2GHz and 75°C, the library that contains the novel gates reduces total power and the number of fins by 36% and 37% respectively, over a conventional library that does not have novel gates in the 32nm technology

Novel dual-Vth independent-gate FinFET circuits

This paper describes gate work function and oxide thickness tuning to realize novel circuits using dual-Vth independent-gate FinFETs. Dual-Vth FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternatives. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional forms, e.g., implementing 12 unique Boolean functions using only four transistors. The gates are designed and calibrated using the University of Florida double-gate model into a technology library. Synthesis results for 14 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average, the enhanced library reduces delay, power, and area by 9%, 21%, and 27%, respectively, over a conventional library designed using FinFETs in 32nm technology.NSF CAREER Award CCF-074685

Performance Analysis of CMOS and FinFET based 16-Bit Barrel Shifter

A barrel shifter shifts ‘n’ number of bits in one cycle. Barrel shifter can perform the following functions: shift left logical, shift left arithmetic, rotate left, shift right logical, shift right arithmetic and rotate right. The design of the barrel shifter is purely MUX based will improve its efficiency if Mux consumes less power. The MUX based SLC barrel shifter circuits are designed using Tanner EDA tools. Fin-type field-effect transistors ( FinFETs) are promising substitutes for bulk CMOS in nano - scale circuits. This paper compares the performance of barrel shifter using two different technologies on the basis of power consumption, time delay and power delay product DOI: 10.17762/ijritcc2321-8169.15067

CMOS Logic Design with FINFETS Using 32nm TECHNOLOGY

In this paper we propose double gate transistor i.e. FINFETS circuits. It is the substitute of bulk CMOS that mean without any compromise in fabrication process except one or two changes. Actually bulk CMOS suffers high power consumption and high leakage currents .so we implement a various novel circuits i.e FINFETS logic design style in 32nm technology and analyzing various parameters like power dissipation, delay, frequency are observed in this paper. In here we notice that less power consumption in FINFETS when compared to ordinary bulk CMOS. We also check the other submicron technology compared to that this submicron technology got less power consumption

Simulation study of vertically stacked lateral Si nanowires transistors for 5 nm CMOS applications

In this paper we present a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5nm CMOS technology. Our simulation approach is based on a collection of simulation techniques to capture the complexity in such ultra-scaled devices. Initially, we used drift-diffusion methodology with activated Poisson-Schrodinger quantum corrections to accurately capture the quantum confinement in the cross-section of the device. Ensemble Monte Carlo simulations are used to accurately evaluate the drive current capturing the complexity of the carrier transport in the NWTs. We compared the current flow in single, double, and triple vertically stacked lateral NWTs with and without contact resistance. The results presented here suggest a consistent link between channel strain and device performance. Furthermore, we propose a device structure for the 5nm CMOS technology node that meets the required industry scaling projection. We also consider the interplay between various sources of statistical variability and reliability in this work

A NOVEL DOUBLE GATE FINFET TRANSISTOR: OPTIMIZED POWER AND PERFORMANCE ANALYSIS FOR EMERGING NANOTECHNOLOGIES

Abstract—FinFET technology has been proposed as a promising alternative for deep sub-micron CMOS technology,because of its superior device performance, scalability, lower leakage power consumption and cost-effective fabricationprocess. Fin-type field-effect transistors (FinFETs) are capable substitutes for bulk CMOS at the nano-scale. Previous workshave studied the performance or power advantages of FinFET circuits over bulk CMOS circuits. This paper elucidates thedependability analysis of Average power, Leakage power, Leakage current and Delay of AND gate using double gateFinFET. Our experiments compare FinFET circuits at different voltages at 45 nm technology in virtuoso tool of cadence,showing that DG FinFET circuits have better dependability and scalability.Keywords—double gate FinFET; fin width; low power circuit; device analysi

Comparing the impact of power supply voltage on CMOS-and FinFET-based SRAMs in the presence of resistive defects

CMOS technology scaling has reached its limit at the 22 nm technology node due to several factors including Process Variations (PV), increased leakage current, Random Dopant Fluctuation (RDF), and mainly the Short-Channel Effect (SCE). In order to continue the miniaturization process via technology down-scaling while preserving system reliability and performance, Fin Field-Effect Transistors (FinFETs) arise as an alternative to CMOS transistors. In parallel, Static Random-Access Memories (SRAMs) increasingly occupy great part of Systems-on-Chips’ (SoCs) silicon area, making their reliability an important issue. SRAMs are designed to reach densities at the limit of the manufacturing process, making this component susceptible to manufacturing defects, including the resistive ones. Such defects may cause dynamic faults during the circuits’ lifetime, an important cause of test escape. Thus, the identification of the proper faulty behavior taking different operating conditions into account is considered crucial to guarantee the development of more suitable test methodologies. In this context, a comparison between the behavior of a 22 nm CMOS-based and a 20 nm FinFET-based SRAM in the presence of resistive defects is carried out considering different power supply voltages. In more detail, the behavior of defective cells operating under different power supply voltages has been investigated performing SPICE simulations. Results show that the power supply voltage plays an important role in the faulty behavior of both CMOS- and FinFET-based SRAM cells in the presence of resistive defects but demonstrate to be more expressive when considering the FinFET-based memories. Studying different operating temperatures, the results show an expressively higher occurrence of dynamic faults in FinFET-based SRAMs when compared to CMOS technology

Benchmarking the screen-grid field effect transistor (SGrFET) for digital applications

Continuous scaling of CMOS technology has now reached a state of evolution, therefore, novel device structures and new materials have been proposed for this purpose. The Screen- Grid field Effect Transistor is introduced as a as a novel device structure that takes advantage of several innovative aspects of the FinFET while introducing new geometrical feature to improve a FET device performance. The idea is to design a FET which is as small as possible without down-scaling issues, at the same time satisfying optimum device performance for both analogue and digital applications. The analogue operation of the SGrFET shows some promising results which make it interesting to continue the investigation on SGrFET for digital applications. The SGrFET addresses some of the concerns of scaled CMOS such as Drain Induce Barrier Lowering and sub-threshold slope, by offering the superior short channel control. In this work in order to evaluate SGrFET performance, the proposed device compared to the classical MOSFET and provides comprehensive benchmarking with finFETs. Both AC and DC simulations are presented using TaurusTM and MediciTM simulators which are commercially available via Synopsis. Initial investigation on the novel device with the single gate structure is carried out. The multi-geometrical characteristic of the proposed device is used to reduce parasitic capacitance and increase ION/IOFF ratio to improve device performance in terms of switching characteristic in different circuit structures. Using TaurusTM AC simulation, a small signal circuit is introduced for SGrFET and evaluated using both extracted small signal elements from TaurusTM and Y-parameter extraction. The SGrFET allows for the unique behavioural characteristics of an independent-gate device. Different configurations of double-gate device are introduced and benchmark against the finFET serving as a double gate device. Five different logic circuits, the complementary and N-inverter, the NOR, NAND and XOR, and controllable Current Mirror circuits are simulated with finFET and SGrFET and their performance compared. Some digital key merits are extracted for both finFET and SGrFET such as power dissipation, noise margin and switching speed to compare the devices under the investigation performance against each other. It is shown that using multi-geometrical feature in SGrFET together with its multi-gate operation can greatly decrease the number of device needed for the logic function without speed degradation and it can be used as a potential candidate in mix-circuit configuration as a multi-gate device. The initial fabrication steps of the novel device explained together with some in-house fabrication process using E-Beam lithography. The fabricated SGrFET is characterised via electrical measurements and used in a circuit configuration

ENERGY-EFFICIENT AND SECURE HARDWARE FOR INTERNET OF THINGS (IoT) DEVICES

Internet of Things (IoT) is a network of devices that are connected through the Internet to exchange the data for intelligent applications. Though IoT devices provide several advantages to improve the quality of life, they also present challenges related to security. The security issues related to IoT devices include leakage of information through Differential Power Analysis (DPA) based side channel attacks, authentication, piracy, etc. DPA is a type of side-channel attack where the attacker monitors the power consumption of the device to guess the secret key stored in it. There are several countermeasures to overcome DPA attacks. However, most of the existing countermeasures consume high power which makes them not suitable to implement in power constraint devices. IoT devices are battery operated, hence it is important to investigate the methods to design energy-efficient and secure IoT devices not susceptible to DPA attacks. In this research, we have explored the usefulness of a novel computing platform called adiabatic logic, low-leakage FinFET devices and Magnetic Tunnel Junction (MTJ) Logic-in-Memory (LiM) architecture to design energy-efficient and DPA secure hardware. Further, we have also explored the usefulness of adiabatic logic in the design of energy-efficient and reliable Physically Unclonable Function (PUF) circuits to overcome the authentication and piracy issues in IoT devices. Adiabatic logic is a low-power circuit design technique to design energy-efficient hardware. Adiabatic logic has reduced dynamic switching energy loss due to the recycling of charge to the power clock. As the first contribution of this dissertation, we have proposed a novel DPA-resistant adiabatic logic family called Energy-Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL). EE-SPFAL based circuits are energy-efficient compared to the conventional CMOS based design because of recycling the charge after every clock cycle. Further, EE-SPFAL based circuits consume uniform power irrespective of input data transition which makes them resilience against DPA attacks. Scaling of CMOS transistors have served the industry for more than 50 years in providing integrated circuits that are denser, and cheaper along with its high performance, and low power. However, scaling of the transistors leads to increase in leakage current. Increase in leakage current reduces the energy-efficiency of the computing circuits,and increases their vulnerability to DPA attack. Hence, it is important to investigate the crypto circuits in low leakage devices such as FinFET to make them energy-efficient and DPA resistant. In this dissertation, we have proposed a novel FinFET based Secure Adiabatic Logic (FinSAL) family. FinSAL based designs utilize the low-leakage FinFET device along with adiabatic logic principles to improve energy-efficiency along with its resistance against DPA attack. Recently, Magnetic Tunnel Junction (MTJ)/CMOS based Logic-in-Memory (LiM) circuits have been explored to design low-power non-volatile hardware. Some of the advantages of MTJ device include non-volatility, near-zero leakage power, high integration density and easy compatibility with CMOS devices. However, the differences in power consumption between the switching of MTJ devices increase the vulnerability of Differential Power Analysis (DPA) based side-channel attack. Further, the MTJ/CMOS hybrid logic circuits which require frequent switching of MTJs are not very energy-efficient due to the significant energy required to switch the MTJ devices. In the third contribution of this dissertation, we have investigated a novel approach of building cryptographic hardware in MTJ/CMOS circuits using Look-Up Table (LUT) based method where the data stored in MTJs are constant during the entire encryption/decryption operation. Currently, high supply voltage is required in both writing and sensing operations of hybrid MTJ/CMOS based LiM circuits which consumes a considerable amount of energy. In order to meet the power budget in low-power devices, it is important to investigate the novel design techniques to design ultra-low-power MTJ/CMOS circuits. In the fourth contribution of this dissertation, we have proposed a novel energy-efficient Secure MTJ/CMOS Logic (SMCL) family. The proposed SMCL logic family consumes uniform power irrespective of data transition in MTJ and more energy-efficient compared to the state-of-art MTJ/ CMOS designs by using charge sharing technique. The other important contribution of this dissertation is the design of reliable Physical Unclonable Function (PUF). Physically Unclonable Function (PUF) are circuits which are used to generate secret keys to avoid the piracy and device authentication problems. However, existing PUFs consume high power and they suffer from the problem of generating unreliable bits. This dissertation have addressed this issue in PUFs by designing a novel adiabatic logic based PUF. The time ramp voltages in adiabatic PUF is utilized to improve the reliability of the PUF along with its energy-efficiency. Reliability of the adiabatic logic based PUF proposed in this dissertation is tested through simulation based temperature variations and supply voltage variations