CMOS SPADs selection, modeling and characterization towards image sensors implementation

The selection, modeling and characterization of Single Photon Avalanche Diodes (SPADs) are presented. Working with the standard 180nm UMC CMOS process, different SPAD structures are proposed in combination with several quenching circuits in order to compare their relative performances. Various configurations for the active region and the prevention of the premature edge breakdown are tested, looking for a miniaturization of the devices to implement image sensor arrays without loses in their performance

A CMOS 8×8 SPAD array for Time-of-Flight measurement and light-spot statistics

The design and simulation of a CMOS 8 × 8 single photon avalanche diode (SPAD) array is presented. The chip has been fabricated in a 0.18μm standard CMOS technology and implements a double functionality: measuring the Time-of-Flight with the help of a pulsed light source; or computing focal-plane statistics in biomedical imaging applications based on a concentrated light-spot. The incorporation of on-chip processing simplifies the interfacing of the array with the host system. The pixel pitch is 32μm, while the diameter of the quasi-circular active area of the SPADs is 12μm. The 113μm 2 active area is surrounded by a T-well guard ring. The resulting breakdown voltage is 10V with a maximum excess voltage of 1.8V. The pixel incorporates a novel active quenching/reset circuit. The array has been designed to operate with a laser pulsed at 20Mhz. The overall time resolution is 115ps. Focal-plane statistics are obtained in digital format. The maximum throughput of the digital output buffers is 200Mbps.Ministerio de Economía y Competitividad IPT-2011-1625- 430000, IPC-20111009Office of Naval Research (USA) N00014111031

Monolithic Perimeter Gated Single Photon Avalanche Diode Based Optical Detector in Standard CMOS

Since the 1930\u27s photomultiplier tubes (PMTs) have been used in single photon detection. Single photon avalanche diodes (SPADs) are p-n junctions operated in the Geiger mode. Unlike PMTs, CMOS based SPADs are smaller in size, insensitive to magnetic fields, less expensive, less temperature dependent, and have lower bias voltages. Using appropriate readout circuitry, they measure properties of single photons, such as energy, arrival time, and spatial path making them excellent candidates for single photon detection. CMOS SPADs suffer from premature breakdown due to the non-uniform distribution of the electric field. This prevents full volumetric breakdown of the device and reduces the detection effciency by increasing the noise. A novel device known as the perimeter gated SPAD (PGSPAD) is adopted in this dissertation for mitigating the premature perimeter breakdown without compromising the fill-factor of the device. The novel contributions of this work are as follows. A novel simulation model, including SPICE characteristics and the stochastic behavior, has been developed for the perimeter gated SPAD. This model has the ability to simulate the static current-voltage and dynamic response characteristics. It also simulates the noise and spectral response. A perimeter gated silicon photomultiplier, with improved signal to noise ratio, is reported for the first time. The gate voltage reduces the dark current of the silicon photomultiplier by preventing the premature breakdown. A digital SPAD with the tunable dynamic range and sensitivity is demonstrated for the first time. This pixel can be used for weak optical signal application when relatively higher sensitivity and lower input dynamic range is required. By making the sensitivity-dynamic range trade-off the same detector can be used for applications with relatively higher optical power. Finally, an array has been developed using the digital silicon photomultiplier in which the dead time of the pixels have been reduced. This digital photomultiplier features noise variation compensation between the pixels

INTEGRATED SINGLE-PHOTON SENSING AND PROCESSING PLATFORM IN STANDARD CMOS

Practical implementation of large SPAD-based sensor arrays in the standard CMOS process has been fraught with challenges due to the many performance trade-offs existing at both the device and the system level [1]. At the device level the performance challenge stems from the suboptimal optical characteristics associated with the standard CMOS fabrication process. The challenge at the system level is the development of monolithic readout architecture capable of supporting the large volume of dynamic traffic, associated with multiple single-photon pixels, without limiting the dynamic range and throughput of the sensor. Due to trade-offs in both functionality and performance, no general solution currently exists for an integrated single-photon sensor in standard CMOS single photon sensing and multi-photon resolution. The research described herein is directed towards the development of a versatile high performance integrated SPAD sensor in the standard CMOS process. Towards this purpose a SPAD device with elongated junction geometry and a perimeter field gate that features a large detection area and a highly reduced dark noise has been presented and characterized. Additionally, a novel front-end system for optimizing the dynamic range and after-pulsing noise of the pixel has been developed. The pixel is also equipped with an output interface with an adjustable pulse width response. In order to further enhance the effective dynamic range of the pixel a theoretical model for accurate dead time related loss compensation has been developed and verified. This thesis also introduces a new paradigm for electrical generation and encoding of the SPAD array response that supports fully digital operation at the pixel level while enabling dynamic discrete time amplitude encoding of the array response. Thus offering a first ever system solution to simultaneously exploit both the dynamic nature and the digital profile of the SPAD response. The array interface, comprising of multiple digital inputs capacitively coupled onto a shared quasi-floating sense node, in conjunction with the integrated digital decoding and readout electronics represents the first ever solid state single-photon sensor capable of both photon counting and photon number resolution. The viability of the readout architecture is demonstrated through simulations and preliminary proof of concept measurements

Geiger-Mode Avalanche Photodiodes in Standard CMOS Technologies

Photodiodes are the simplest but most versatile semiconductor optoelectronic devices. They can be used for direct detection of light, of soft X and gamma rays, and of particles such as electrons or neutrons. For many years, the sensors of choice for most research and industrial applications needing photon counting or timing have been vacuum-based devices such as Photo-Multiplier Tubes, PMT, and Micro-Channel Plates, MCP (Renker, 2004). Although these photodetectors provide good sensitivity, noise and timing characteristics, they still suffer from limitations owing to their large power consumption, high operation voltages and sensitivity to magnetic fields, as well as they are still bulky, fragile and expensive. New approaches to high-sensitivity imagers tend to use CCD cameras coupled with either MCP Image Intensifiers, I-CCDs, or Electron Multipliers, EM-CCDs (Dussault & Hoess, 2004), but they still have limited performances in extreme time-resolved measurements. A fully solid-state solution can improve design flexibility, cost, miniaturization, integration density, reliability and signal processing capabilities in photodetectors. In particular, Single- Photon Avalanche Diodes, SPADs, fabricated by conventional planar technology on silicon can be used as particle (Stapels et al., 2007) and photon (Ghioni et al., 2007) detectors with high intrinsic gain and speed. These SPAD are silicon Avalanche PhotoDiodes biased above breakdown. This operation regime, known as Geiger mode, gives excellent single-photon sensitivity thanks to the avalanche caused by impact ionization of the photogenerated carriers (Cova et al., 1996). The number of carriers generated as a result of the absorption of a single photon determines the optical gain of the device, which in the case of SPADs may be virtually infinite. The basic concepts concerning the behaviour of G-APDs and the physical processes taking place during their operation will be reviewed next, as well as the main performance parameters and noise sources

The Quanta Image Sensor: Every Photon Counts

The Quanta Image Sensor (QIS) was conceived when contemplating shrinking pixel sizes and storage capacities, and the steady increase in digital processing power. In the single-bit QIS, the output of each field is a binary bit plane, where each bit represents the presence or absence of at least one photoelectron in a photodetector. A series of bit planes is generated through high-speed readout, and a kernel or “cubicle” of bits (x, y, t) is used to create a single output image pixel. The size of the cubicle can be adjusted post-acquisition to optimize image quality. The specialized sub-diffraction-limit photodetectors in the QIS are referred to as “jots” and a QIS may have a gigajot or more, read out at 1000 fps, for a data rate exceeding 1 Tb/s. Basically, we are trying to count photons as they arrive at the sensor. This paper reviews the QIS concept and its imaging characteristics. Recent progress towards realizing the QIS for commercial and scientific purposes is discussed. This includes implementation of a pump-gate jot device in a 65 nm CIS BSI process yielding read noise as low as 0.22 e− r.m.s. and conversion gain as high as 420 µV/e−, power efficient readout electronics, currently as low as 0.4 pJ/b in the same process, creating high dynamic range images from jot data, and understanding the imaging characteristics of single-bit and multi-bit QIS devices. The QIS represents a possible major paradigm shift in image capture

Ultra-Low-Temperature Silicon and Germanium-on-Silicon Avalanche Photodiodes:Modeling, Design, and Characterization

In this thesis we propose the use of photodiodes fabricated in planar technologies to address the detection problem in these applications. A number of solutions exist, optimized for these wavelengths, based on Germanium (Ge) and other III-V materials. In this thesis we focused on Ge thanks to its versatility and ease to use in the clean room. The main advantage of this material is in fact a good compatibility with Silicon and standard CMOS processes. Note that the proposed technology is not based on Silicon/Germanium (SiGe), whereby Ge is used to strain Si to achieve higher bandwidth in Si, not higher sensitivity. In our pure Ge approach, Ge is grafted onto Si (Ge-on-Si), achieving high responsivity at wavelengths of 900nm and higher. The proposed devices can operate in avalanche mode (avalanche photodiodes - APDs), and in Geiger mode (Geiger mode APDs (GAPDs) or single-photon avalanche diodes (SPADs)). To combine the advantages of Ge with single-photon sensitivity and excellent timing resolution of Si-based SPADs, this thesis proposes a new generation of SPADs, achieved in collaboration with Prof. Nanver at TUDelft, aimed at near-infrared range. The fabrication process of the Ge-on-Si SPAD approach, which we are investigating together with the TUDelft group, consists of a standard CMOS process combined with post-processing steps to grow Ge on top of a Si/SiO2 layer. In our study we have investigated the potential for a new generation of massively parallel, Ge-on-Si sensors fabricated in fully CMOS compatible technology. The objective was to address the next challenges of super-parallel pixel arrays, while exploiting the advantages of Ge substrate. The key technology developed in the thesis is a selective chemical-vapor deposition (CVD) epitaxial growth. A novel processing procedure was developed for the p+ Ge surface doping by a sequence of pure-Ga and pure-B depositions (PureGaB). The resulting p+n diodes have exceptionally good I-V characteristics with ideality factor of ~1.1 and low saturation currents. They can be operated both in proportional and in Geiger mode, and exhibit relatively low dark counts. We also looked at techniques to improve red and infrared sensitivity in conventional deep-submicron CMOS processes, by careful selection of standard layers at high depths in the Si substrate. Using the proposed approach, 12 µm-diameter SPADs were fabricated in 0.18µm CMOS technology showing low dark count rates (363 cps) at room temperature and considerably lower rates at cryogenic temperatures (77 K), while the FWHM timing jitter is as low as 76 ps. That of cryogenic SPADs is a novel research direction and in this thesis it was advocated as a significant trend for the future of optical sensing, especially in mid-infrared wavelengths. Low temperature characterizations reported in this thesis exposed how the relevant properties of fabrication materials, such as strength, thermal conductivity, ductility, and electrical resistance are changing. One of the most important properties is superconductivity in materials cooled to extreme temperatures: this is an important trend that will be pursued in the future activities of our group

Design of CMOS Digital Silicon Photomultipliers with ToF for Positron Emission Tomography

This thesis presents a contribution to the design of single-photon detectors for medical imaging. Specifically, the focus has been on the development of a pixel capable of single-photon counting in CMOS technology, and the associated sensor thereof. These sensors can work under low light conditions and provide timing information to determine the time-stamp of the incoming photons. For instance, this is particularly attractive for applications that rely either on time-of-flight measurements or on exponential decay determination of the light source, like positron emission tomography or fluorescence-lifetime imaging, respectively. This thesis proposes the study of the pixel architecture to optimize its performance in terms of sensitivity, linearity and signal to noise ratio. The design of the pixel has followed a bottom-up approach, taking care of the smallest building block and studying how the different architecture choices affect performance. Among the various building blocks needed, special emphasis has been placed on the following: • the Single-Photon Avalanche Diode (SPAD), a photodiode able to detect photons one by one; • the front-end circuitry of this diode, commonly called quenching and recharge circuit; • the Time-to-Digital Converter (TDC), which determines the timing performance of the pixel. The proposed architectural exploration provides a comprehensive insight into the design space of the pixel, allowing to determine the optimum design points in terms of sensor sensitivity, linearity or signal to noise ratio, thus helping designers to navigate through non-straightforward trade-offs. The proposed TDC is based on a voltage-controlled ring oscillator, since this architecture provides moderate time resolutions while keeping the footprint, the power, and conversion time relatively small. Two pseudo-differential delay stages have been studied, one with cross-coupled PMOS transistors and the other with cross-coupled inverters. Analytical studies and simulations have shown that cross-coupled inverters are the most appropriate to implement the TDC because they achieve better time resolution with smaller energy per conversion than cross-coupled PMOS transistor stages. A 1.3×1.3 mm2 pixel has been implemented in an 110 nm CMOS image sensor technology, to have the benefits of sub-micron technologies along with the cleanliness of CMOS image sensor technologies. The fabricated chips have been used to characterize the single-photon avalanche diodes. The results agree with expectations: a maximum photon detection probability of 46 % and a median dark count rate of 0.4 Hz/µm2 with an excess voltage of 3 V. Furthermore, the characterization of the TDC shows that the time resolution is below 100 ps, which agrees with post-layout simulations. The differential non-linearity is ±0.4LSB, and the integral non-linearity is ±6.1LSB. Photoemission occurs during characterization - an indication that the avalanches are not quenched properly. The cause of this has been identified to be in the design of the SPAD and the quenching circuit. SPADs are sensitive devices which maximum reverse current must be well defined and limited by the quenching circuit, otherwise unwanted effects like excessive cross-talk, noise, and power consumption may happen. Although this issue limits the operation of the implemented pixel, the information obtained during the characterization will help to avoid mistakes in future implementations

Imaging Probe for Charged Particle Detection

Single Photon Avalanche Diodes (SPADs) are semiconductor devices that detect individual photons. However, they can also experience dark count rate (DCR), generating avalanche current even when no photons are present, which limits their ability to detect low-level signals. SPADs characterization is important to gain insight into their behavior and improve their performance for various applications. This thesis discusses the development of a portable detection probe that uses the APIX2LF chip, which contains arrays of SPADs that were produced using a 150 nm standard CMOS process. A prototype board, that includes a battery, front-end electronics, and a microcontroller acting as the interface between the sensor and the PC was developed and tested using a beta-emitting source. Additionally, custom firmware was designed for the microcontroller and an automatic data acquisition framework was developed for the characterization of the DCR of six APIX2LF chips at different bias voltages and temperatures.This thesis discusses the development of a portable detection probe that uses the APIX2LF chip, which contains arrays of SPADs that were produced using a 150 nm standard CMOS process. A prototype board, that includes a battery, front-end electronics, and a microcontroller acting as the interface between the sensor and the PC was developed and tested using a beta-emitting source. Additionally, custom firmware was designed for the microcontroller and an automatic data acquisition framework was developed for the characterization of the DCR of six APIX2LF chips at different bias voltages and temperatures

Challenges and Solutions to Next-Generation Single-Photon Imagers

Detecting and counting single photons is useful in an increasingly large number of applications. Most applications require large formats, approaching and even far exceeding 1 megapixel. In this thesis, we look at the challenges of massively parallel photon-counting cameras from all performance angles. The thesis deals with a number of performance issues that emerge when the number of pixels exceeds about 1/4 of megapixels, proposing characterization techniques and solutions to mitigate performance degradation and non-uniformity. Two cameras were created to validate the proposed techniques. The first camera, SwissSPAD, comprises an array of 512 x 128 SPAD pixels, each with a one-bit memory and a gating mechanism to achieve 5ns high precision time windows with high uniformity across the array. With a massively parallel readout of over 10 Gigabit/s and positioning of the integration time window accurate to the pico-second range, fluorescence lifetime imaging and fluorescence correlation spectroscopy imaging achieve a speedup of several orders of magnitude while ensuring high precision in the measurements. Other possible applications include wide-field time-of-flight imaging and the generation of quantum random numbers at highest bit-rates. Lately super-resolution microscopy techniques have also used SwissSPAD. The second camera, LinoSPAD, takes the concepts of SwissSPAD one step further by moving even more 'intelligence' to the FPGA and reducing the sensor complexity to the bare minimum. This allows focusing the optimization of the sensor on the most important metrics of photon efficiency and fill factor. As such, the sensor consists of one line of SPADs that have a direct connection each to the FPGA where complex photon processing algorithms can be implemented. As a demonstration of the capabilities of current lowcost FPGAs we implemented an array of time-to-digital converters that can handle up to 8.5 billion photons per second, measuring each one of them and accounting them in high precision histograms. Using simple laser diodes and a circuit to generate light pulses in the picosecond range, we demonstrate a ubiquitous 3D time-of-flight sensor. The thesis intends to be a first step towards achieving the world's first megapixel SPAD camera, which, we believe, is in grasp thanks to the architectural and circuital techniques proposed in this thesis. In addition, we believe that the applications proposed in this thesis offer a wide variety of uses of the sensors presented in this thesis and in future ones to come