6,399 research outputs found

    CMOS로 제어되는 GaN HEMT Supply Modulator를 이용한 고효율 Average Power Tracking 전력 증폭기

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    학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 8. 권영우.본 논문에서는 Cree사의 CGH60시리즈 GaN HEMT bare die칩으로 제작된 PA를 이용한 Average Power Tracking (APT) 시스템이 구현되었다. 전원 변조기의 제어 회로로써 IBM 0.18um SOI 2.5V RF 공정이 사용되었다. 전원 변조기로는 Class E2 DC-DC컨버터가 사용되었다. Class-E 인버터와 Class-E정류기에 필요한 스위치로는 GaN HEMT가 사용되었다. 두 스위치 모두 CMOS회로에서 펄스 폭 변조 (PWM)방식으로 만들어진 펄스로 제어되었다. 공급 전압 28V와 1MHz PWM신호를 사용한 결과 듀티가 0.5일 때 최대 효율 85%와 31V의 출력 전압을 얻을 수 있었다. GaN HEMT를 이용하여 5.8GHz 고효율 2-단 Class-E 전력 증폭기도 제작되었다. 수치 해석적으로 초기 디자인이 진행되었으며, lumped 소자들은 모두 마이크로스트립으로 대체되었다. 측정 결과 39dBm에서 63.9%의 효율을 얻을 수 있었으며 그때의 전력 이득은 15.8dB였다. Power-단의 드레인 효율은 76%였다. 백오프 구간에서의 효율을 올리기 위해 APT 시스템이 적용되었다. 시스템의 Power-단 드레인 효율은 6dB 백오프 지점에서 1%증가하였으며 9dB 백오프 지점에서 5.7% 증가하였다. 전원 변조기의 최대 출력 전압은 32V로 부스팅 되기 때문에 최대 출력 전력은 37.9dBm에서 38.7dBm으로 증가하였다. 전원 변조기를 제어하기 위해 펄스 폭과 주파수 변조 (PWFM)방식이 PWM대신 제안되었다. 제안된 전원 변조기는 12V출력전압일 때 11%의 효율 증가를 보여주었으며 따라서 넓은 출력 전압 영역에서 70%이상의 효율을 보여주었다. 같은 PA에 APT를 적용한 결과 39.6dBm에서 최대 PAE 49.5%를 얻을 수 있었다. 6dB와 9dB백오프 지점에서의 효율은 각각 4%와 3.5%씩 증가하였다.In this thesis, an Average Power Tracking (APT) system of a Power Amplifier (PA) using Cree Inc. CGH60 series GaN HEMT bare die is presented. IBM 0.18um SOI 2.5V RF technology is used to fabricate control circuits in supply modulator. A Class E2 DC-DC Converter is adopted as the supply modulator. Both Class-E inverter switch and Class-E rectifier switch uses GaN HEMT as a switch. Both switches are controlled by Pulse Width Modulation (PWM) generated by CMOS control circuit. The peak efficiency is 85% at 31V of output voltage with 0.5 duty cycle of 1MHz PWM when 28V is supplied. Highly efficient 5.8GHz 2-Stage Class-E Power Amplifier is realized with GaN HEMT device. Numerical analysis has performed for initial design of PA then the ideal lumped elements are replaced with microstrip lines. The measurement results show the maximum PAE of 63.9% at 39.0dBm of output power with 15.8dB gain. The maximum power-stage drain efficiency is 76% Average Power Tracking is applied in order to increase power-stage drain efficiency at back-off power. The system shows 1% of drain efficiency increment at 6-dB back-off and 5.7% increment at 9-dB back-off power. Since the supply modulator boosts up to 32-V, the maximum output power is increased to 38.7dBm from 37.9dBm. Pulse Width and Frequency Modulation (PWFM) control method is introduced in place PWM control in supply modulator. The new supply modulator shows 11% of efficiency increment at 12V resulting in higher than 70% of efficiency over wide output voltage range. When Average Power Tracking is applied with the same PA, the peak PAE of 49.5% at 39.6dBm with gain of 15.6dB is resulted. At 6 dB and 9 dB back-off power, 4% and 3.5% of PAE is increased.Abstract Table of Contents List of Figures List of Tables 1. Introduction 2. Supply Modulator 2.1. Introduction 2.2. Class E2 DC-DC Converter 2.3. PWM Controlled Supply Modulator 2.3.1. Pulse Width Modulation (Inverter Switch Control) 2.3.2. Rectifier Switch Control 2.4. CMOS Control Circuit 2.4.1. Operational Amplifier 2.4.2. Comparator 2.4.3. Hysteresis Comparator 2.4.4. Voltage Regulator 2.4.5. Gate Driver 2.4.6. Layout 2.5. Measurement: Hybrid Modulator with CMOS and GaN HEMT 2.5.1. CMOS Control Circuit Results 2.5.2. Hybrid Modulator Results 2.6. Future Work 2.7. Conclusion 3. Power Amplifier 3.1. Introduction 3.2. Class E Power Amplifier 3.3. Extraction of Parasitic Elements 3.4. Two-Stage Class-E Power Amplifier 3.4. Measurement: Class E Two Stage Power Amplifier 3.5. Conclusion 4. Average Power Tracking System I 4.1. Introduction 4.2. Expected Overall PAE Calculation 4.3. Synchronization of Supply Modulator with Power Amplifier 4.3. Measurement: Average Power Tracking Power Amplifier I 4.4. Conclusion 5. Average Power Tracking System II 5.1. Introduction 5.2. Concept of PWFM 5.3. Measurement: PWFM Controlled Supply Modulator 5.4. Highly Efficient 5.8GHz Power Amplifier 5.5. Measurement: Average Power Tracking Power Amplifier II 5.6. Conclusion 6. Conclusion Reference Appendix Notes 초록 AcknowledgementMaste

    RF transceiver design for electronic toll collection system (ETC) using compact dipole antenna

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    Electronic Toll Collection (ETC) system is one of the types of traffic control system that has rapid development in the recent years. ETC system is one of the major applications of Dedicated Short Range Communication (DSRC) which operates in the frequency band of 5.8GHz, used for the transfer of information between the road side unit (RSU) and the on board unit (OBU) which are situated at the toll station and on the vehicle respectively. The working of the system is based on RFID technology. ETC system is implemented in the 0.18microm CMOS technology, which is an aggressive technology in terms of its low cost and easy integration of the RF circuits.;A compact dipole antenna based low-cost RF transceiver for ETC system is designed in this thesis. Amplitude Shift Keying (ASK) modulation technique is employed in the implemented RF transceiver. In transmitter side, a class-E power amplifier is used to amplify the signal power. In order to send and receive the signal, a dipole antenna operating at a frequency of 5.8GHz is used. A low-power and energy efficient Low-Noise Amplifier (LNA) is used in the receiver block which consumes very less power and has a minimal noise figure compared with prior arts. A self-mixer is used for the down-conversion of the signal. Results of this design demonstrate the working of the transceiver at 5.8GHz frequency up to an input data rate of 400 Mbps

    Design of 2MHz OOK transmitter/receiver for inductive power and data transmission for biomedical implant

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    In this work a 2 MHz on-off keying (OOK) transmitter/receiver for inductive power and data transmission for biomedical implant system is presented. Inductive link, driven by a Class E power amplifier (PA) is the most PA used to transfer data and power to the internal part of biomedical implant system. Proposed transmitter consists of a digital control oscillator (DCO) and a class E PA which uses OOK modulation to transfer both data and power to a biomedical implant. In proposing OOK transmitter when the transmitter sends binary value “0” the DCO and PA are turned off. With this architecture and 2 MHz carrier wave we have implemented a wireless data and power transfer link which can transmit data with data rate 1Mbps and bit error rate (BER) of 10-5. The efficiency of power transfer is 42% with a 12.7 uH transmitter coil and a 2.4 uH receiver coil and the power delivered to the load is about 104.7 mW. Proposed transmitter is designed for output power 4.1V. OOK receiver consists of an OOK demodulator, powered by rectified and regulated 5V p-p RF signal across the receiver coil. The supply voltage of proposed voltage regulator is 5 V with 9mV/V line regulation of. All circuits proposed in this paper were designed and simulated using Cadence in 0.18 um CMOS process

    A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier

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    Concentric distributed active transformers (DAT) are used to implement a fully-integrated quad-band power amplifier (PA) in a standard 130 nm CMOS process. The DAT enables the power amplifier to integrate the input and output matching networks on the same silicon die. The PA integrates on-chip closed-loop power control and operates under supply voltages from 2.9 V to 5.5 V in a standard micro-lead-frame package. It shows no oscillations, degradation, or failures for over 2000 hours of operation with a supply of 6 V at 135° under a VSWR of 15:1 at all phase angles and has also been tested for more than 2 million device-hours (with ongoing reliability monitoring) without a single failure under nominal operation conditions. It produces up to +35 dBm of RF power with power-added efficiency of 51%

    An Octave-Range, Watt-Level, Fully-Integrated CMOS Switching Power Mixer Array for Linearization and Back-Off-Efficiency Improvement

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    The power mixer array is presented as a novel power generation approach for non-constant envelope signals. It comprises several power mixer units that are dynamically turned on and off to improve the linearity and back-off efficiency. At the circuit level, the power mixer unit can operate as a switching amplifier to achieve high peak power efficiency. Additional circuit level linearization and back-off efficiency improvement techniques are also proposed. To demonstrate the feasibility of this idea, a fully-integrated octave-range CMOS power mixer array is implemented in a 130 nm CMOS process. It is operational between 1.2 GHz and 2.4 GHz and can generate an output power of +31.3 dBm into an external 50 Ω load with a PAE of 42% and a gain compression of only 0.4 dB at 1.8 GHz. It achieves a PAE of 25%, at an average output power of +26.4 dBm, and an EVM of 4.6% with a non-constant-envelope 16 QAM signal. It can also produce arbitrary signal levels down to -70 dBm of output power with the 16 QAM-modulated signal without any RF gain control circuit

    Fully integrated CMOS power amplifier design using the distributed active-transformer architecture

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    A novel on-chip impedance matching and power-combining method, the distributed active transformer is presented. It combines several low-voltage push-pull amplifiers efficiently with their outputs in series to produce a larger output power while maintaining a 50-Ω match. It also uses virtual ac grounds and magnetic couplings extensively to eliminate the need for any off-chip component, such as tuned bonding wires or external inductors. Furthermore, it desensitizes the operation of the amplifier to the inductance of bonding wires making the design more reproducible. To demonstrate the feasibility of this concept, a 2.4-GHz 2-W 2-V truly fully integrated power amplifier with 50-Ω input and output matching has been fabricated using 0.35-μm CMOS transistors. It achieves a power added efficiency (PAE) of 41 % at this power level. It can also produce 450 mW using a 1-V supply. Harmonic suppression is 64 dBc or better. This new topology makes possible a truly fully integrated watt-level gigahertz range low-voltage CMOS power amplifier for the first time

    A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

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    © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

    A fully-integrated 1.8-V, 2.8-W, 1.9-GHz, CMOS power amplifier

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    This paper demonstrated the first 2-stage, 2.8W, 1.8V, 1.9GHz fully-integrated DAT power amplifier with 50Ω input and output matching using 0.18μm CMOS transistors. It has a small-signal gain of 27dB. The amplifier provides 2.8W of power into a 50Ω load with a PAE of 50%
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