5,067 research outputs found
Phononics: Manipulating heat flow with electronic analogs and beyond
The form of energy termed heat that typically derives from lattice
vibrations, i.e. the phonons, is usually considered as waste energy and,
moreover, deleterious to information processing. However, with this colloquium,
we attempt to rebut this common view: By use of tailored models we demonstrate
that phonons can be manipulated like electrons and photons can, thus enabling
controlled heat transport. Moreover, we explain that phonons can be put to
beneficial use to carry and process information. In a first part we present
ways to control heat transport and how to process information for physical
systems which are driven by a temperature bias. Particularly, we put forward
the toolkit of familiar electronic analogs for exercising phononics; i.e.
phononic devices which act as thermal diodes, thermal transistors, thermal
logic gates and thermal memories, etc.. These concepts are then put to work to
transport, control and rectify heat in physical realistic nanosystems by
devising practical designs of hybrid nanostructures that permit the operation
of functional phononic devices and, as well, report first experimental
realizations. Next, we discuss yet richer possibilities to manipulate heat flow
by use of time varying thermal bath temperatures or various other external
fields. These give rise to a plenty of intriguing phononic nonequilibrium
phenomena as for example the directed shuttling of heat, a geometrical phase
induced heat pumping, or the phonon Hall effect, that all may find its way into
operation with electronic analogs.Comment: 24 pages, 16 figures, modified title and revised, accepted for
publication in Rev. Mod. Phy
Improving Instruction Fetch Rate with Code Pattern Cache for Superscalar Architecture
In the past, instruction fetch speeds have been improved by using cache schemes that capture the actual program flow. In this proposal, we present the architecture of a new instruction cache named code pattern cache (CPC); the cache is used with superscalar processors. CPC?s operation is based on the fundamental principles that: common programs tend to repeat their execution patterns; and efficient storage of a program flow can enhance the performance of an instruction fetch mechanism. CPC saves basic blocks (sets of instructions separated by control instructions) and their boundary addresses while the code is running. Basic blocks and their addresses are stored in two separate structures, called block pointer cache (BPC) and basic block cache (BBC), respectively. Later, if the same basic block sequence is expected to execute, it is fetched from CPC, instead of the instruction cache; this mechanism results in higher likelihood of delivering a larger number of instructions in every clock cycle. We developed single and multi-threaded simulators for TC, BC, and CPC, and used them with 10 SPECint2000 benchmarks. The simulation results demonstrated CPC?s advantage over TC and BC, in terms of trace miss rate and average trace length. Additionally, we used cache models to quantify the timing, area, and power for the three cache schemes. Using an aggregate performance index that combined the simulation and modeling results, CPC was shown to perform better than both TC and BC. During our research, each of the TC-, BC-, or CPC- configurations took 4-6 hours to simulate, so performance comparison of these caches proved to be a very time-consuming process. Neural network models (NNM?s) can be time-efficient alternatives to simulations, so we studied their feasibility to represent the cache behavior. We developed two NNM\u27s, one to predict the trace miss rate and the other to predict the average trace length for the three caches. The NNM\u27s modeled the caches with reasonable accuracy, and produced results in a fraction of a second
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Polygenic risk associated with post-traumatic stress disorder onset and severity.
Post-traumatic stress disorder (PTSD) is a psychiatric illness with a highly polygenic architecture without large effect-size common single-nucleotide polymorphisms (SNPs). Thus, to capture a substantial portion of the genetic contribution, effects from many variants need to be aggregated. We investigated various aspects of one such approach that has been successfully applied to many traits, polygenic risk score (PRS) for PTSD. Theoretical analyses indicate the potential prediction ability of PRS. We used the latest summary statistics from the largest published genome-wide association study (GWAS) conducted by Psychiatric Genomics Consortium for PTSD (PGC-PTSD). We found that the PRS constructed for a cohort comprising veterans of recent wars (n = 244) explains a considerable proportion of PTSD onset (Nagelkerke R2 = 4.68%, P = 0.003) and severity (R2 = 4.35%, P = 0.0008) variances. However, the performance on an African ancestry sub-cohort was minimal. A PRS constructed with schizophrenia GWAS also explained a significant fraction of PTSD diagnosis variance (Nagelkerke R2 = 2.96%, P = 0.0175), confirming previously reported genetic correlation between the two psychiatric ailments. Overall, these findings demonstrate the important role polygenic analyses of PTSD will play in risk prediction models as well as in elucidating the biology of the disorder
Elastin-like recombinamers as smart drug delivery systems
Drug delivery systems that are able to control the release of bioactive molecules and designed to carry drugs to target sites are of particular interest for tissue therapy. Moreover, systems comprising materials that can respond to environmental stimuli and promote self-assembly and higher order supramolecular organization are especially useful in the biomedical field. Suitable biomaterials for this purpose include elastin-like recombinamers (ELRs), a class of proteinaceous polymers bioinspired by natural elastin and designed usingrecombinant technologies. The self-assembly and thermoresponsive behaviour of these systems, along with their biodegradability, biocompatibility and well-defined composition as a result of their tailor-made design, make them particularly attractive for drug delivery.Este trabajo forma parte de Proyectos de Investigación financiados por la Comisión Europea a través del Fondo Social Europeo (FSE) y el Fondo Europeo de Desarrollo Regional (ERDF), por el del MINECO (MAT2013-41723R, MAT2013-42473-R, MAT2012-38043 y PRI-PIBAR-2011-1403), la Junta de Castilla y León (VA049A11, VA152A12 y VA155A12) y el Instituto de Salud Carlos III bajo el Centro en Red de Medicina Regenerativa y Terapia Celular de Castilla y León
Cal Poly Supermileage Dynamometer
Our senior project involves designing a chassis dynamometer capable of simulating variable loads for the Cal Poly Supermileage Vehicle (SMV) team. The chassis dynamometer we are developing uses an alternator to develop additional resistance that the vehicle will have to overcome while testing. To implement a control system for the variable load, we use an Arduino Nano paired with multiple sensors and drivers. This control system allows the user to select different levels of resistance that correlate with different road grades. We designed a custom Printed Circuit Board (PCB) that will contain all the electrical components needed for the control system. We designed a mechanical system that makes use of belt drive pulleys to link the resistance provided by the alternator to the rotating drum and shaft assembly. Our final design also includes a software system with a Graphical User Interface (GUI) that allows for users of the SMV team to easily select various road grades and see the results of their dynamometer testing. Our design will allow the SMV team to make more efficient upgrades to the powertrain of both their gas and electric vehicles
Authenticated storage using small trusted hardware
A major security concern with outsourcing data storage to third-party providers is authenticating the integrity and freshness of data. State-of-the-art software-based approaches require clients to maintain state and cannot immediately detect forking attacks, while approaches that introduce limited trusted hardware (e.g., a monotonic counter) at the storage server achieve low throughput. This paper proposes a new design for authenticating data storage using a small piece of high-performance trusted hardware attached to an untrusted server. The proposed design achieves significantly higher throughput than previous designs. The server-side trusted hardware allows clients to authenticate data integrity and freshness without keeping any mutable client-side state. Our design achieves high performance by parallelizing server-side authentication operations and permitting the untrusted server to maintain caches and schedule disk writes, while enforcing precise crash recovery and write access control
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