A Zero Bias Pixel Sensor and its Zero-Bias Column Buffer-Direct-Injection Circuit

Two pixel sensors, namely active pixel sensor (APS) and pseudo-active pixel sensor (PAPS), are reviewed to show that APS suffers from dark current while PAPS suffers from leakage current. Then a new pixel sensor called  zero bias pixel sensor (ZBPS) in which only two MOS switches in addition to the photodiode are used, one for connecting the pixel’s photodiode to a column bus and the other for bypassing it. A zero-bias column buffer-direct-injection (ZCBDI) circuit, which is similar to a regulated cascode amplifier, is used to control the voltage at column bus at zero. All ZBPS pixels are guaranteed to work at zero voltage at all times to eliminate the dark current as well as leakage current. A case of a 10 µm x 10 µm ZBPS pixel designed with standard 0.18 µm CMOS process is studied through simulation. This pixel generates a photocurrent within a range from 1 pA to 100 nA. To handle a large variation of photocurrent while maintaining zero column voltage, the ZCBDI is designed using differential cascode, common source, and buffer stages and then compensated for 50 degree phase margin. Transient simulation shows that the pixel steady state response time is around 1.406 ms, leading to at most 5.5 frames per second for an image of 128 x 128 ZBPS pixels. The fill factor of ZBPS for this case is around 59%

MOSFET Modulated Dual Conversion Gain CMOS Image Sensors

In recent years, vision systems based on CMOS image sensors have acquired significant ground over those based on charge-coupled devices (CCD). The main advantages of CMOS image sensors are their high level of integration, random accessibility, and low-voltage, low-power operation. Previously proposed high dynamic range enhancement schemes focused mainly on extending the sensor dynamic range at the high illumination end. Sensor dynamic range extension at the low illumination end has not been addressed. Since most applications require low-noise, high-sensitivity, characteristics for imaging of the dark region as well as dynamic range expansion to the bright region, the availability of a low-noise, high-sensitivity pixel device is particularly important. In this dissertation, a dual-conversion-gain (DCG) pixel architecture was proposed; this architecture increases the signal to noise ratio (SNR) and the dynamic range of CMOS image sensors at both the low and high illumination ends. The dual conversion gain pixel improves the dynamic range by changing the conversion gain based on the illumination level without increasing artifacts or increasing the imaging readout noise floor. A MOSFET is used to modulate the capacitance of the charge sensing node. Under high light illumination conditions, a low conversion gain is used to achieve higher full well capacity and wider dynamic range. Under low light conditions, a high conversion gain is enabled to lower the readout noise and achieve excellent low light performance. A sensor prototype using the new pixel architecture with 5.6μm pixel pitch was designed and fabricated using Micron Technology’s 130nm 3-metal and 2-poly silicon process. The periphery circuitries were designed to readout the pixel and support the pixel characterization needs. The pixel design, readout timing, and operation voltage were optimized. A detail sensor characterization was performed; a 127μV/e was achieved for the high conversion gain mode and 30.8μV/e for the low conversion gain mode. Characterization results confirm that a 42ke linear full well was achieved for the low conversion gain mode and 10.5ke for the high conversion gain mode. An average 2.1e readout noise was measured for the high conversion gain mode and 8.6e for the low conversion gain mode. The total sensor dynamic range was extended to 86dB by combining the two modes of operation with a 46.2dB maximum SNR. Several images were taken by the prototype sensor under different illumination levels. The simple processed color images show the clear advantage of the high conversion gain mode for the low light imaging

Analysis and design of a wide dynamic range pulse-frequency modulation CMOS image sensor

Complementary Metal-Oxide Semiconductor (CMOS) image sensor is the dominant electronic imaging device in many application fields, including the mobile or portable devices, teleconference cameras, surveillance and medical imaging sensors. Wide dynamic range (WDR) imaging is of interest particular, demonstrating a large-contrast imaging range of the sensor. As of today, different approaches have been presented to provide solutions for this purpose, but there exists various trade-offs among these designs, which limit the number of applications. A pulse-frequency modulation (PFM) pixel offers the possibility to outperform existing designs in WDR imaging applications, however issues such as uniformity and cost have to be carefully handled to make it practical for different purposes. In addition, a complete evaluation of the sensor performance has to be executed prior to fabrication in silicon technology. A thorough investigation of WDR image sensor based on the PFM pixel is performed in this thesis. Starting with the analysis, modeling, and measurements of a PFM pixel, the details of every particular circuit operation are presented. The causes of dynamic range (DR) limitations and signal nonlinearity are identified, and noise measurement is also performed, to guide future design strategies. We present the design of an innovative double-delta compensating (DDC) technique which increases the sensor uniformity as well as DR. This technique achieves performance optimization of the PFM pixel with a minimal cost an improved linearity, and is carefully simulated to demonstrate its feasibility. A quad-sampling technique is also presented with the cooperation of pixel and column circuits to generate a WDR image sensor with a reduced cost for the pixel. This method, which is verified through the field-programmable gate array (FPGA) implementation, saves considerable area in the pixel and employs the maximal DR that a PFM pixel provides. A complete WDR image sensor structure is proposed to evaluate the performance and feasibility of fabrication in silicon technology. The plans of future work and possible improvements are also presented

Speckle pattern interferometry : vibration measurement based on a novel CMOS camera

A digital speckle pattern interferometer based on a novel custom complementary metaloxide- semiconductor (CMOS) array detector is described. The temporal evolution of the dynamic deformation of a test object is measured using inter-frame phase stepping. The flexibility of the CMOS detector is used to identify regions of interest with full-field time averaged measurements and then to interrogate those regions with time-resolved measurements sampled at up to 7 kHz. The maximum surface velocity that can be measured and the number of measurement points are limited by the frame rate and the data transfer rate of the detector. The custom sensor used in this work is a modulated light camera (MLC), whose pixel design is still based on the standard four transistor active pixel sensor (APS), but each pixel has four large independently shuttered capacitors that drastically boost the well capacity from that of the diode alone. Each capacitor represents a channel which has its own shutter switch and can either be operated independently or in tandem with others. The particular APS of this camera enables a novel approach in how the data are acquired and then processed. In this Thesis we demonstrate how, at a given frame rate and at a given number of measurement points, the data transfer rate of our system is increased if compared to the data transfer rate of a system using a standard approach. Moreover, under some assumptions, the gain in system bandwidth doesn’t entail any reduction in the maximum surface velocity that can be reliably measured with inter-frame phase stepping

Noise Characterization of a CMOS X-Ray Image Sensor

The objective of this thesis is to validate the noise performance of a high resolution CMOS X-ray imager. We carry out a detailed noise analysis on a four-quadrant CMOS imager and the external hardware. Careful analysis reveals several design issues on the printed circuit board (PCB). We propose solutions to improve the PCB design. Experimental results show the modified system outperforms the original one with a sizable margi

Pixellated radiation detectors for scientific applications

The work in this thesis is focused on characterisation and evaluation of two classes of science grade imaging radiation detectors. The first class is Monolithic Active Pixel Sensors (MAPS). The advances in CMOS fabrication technologies over the last four decades allowed MAPS to compete with Charge-Coupled Devices (CCD) in many applications. The technology also provides relatively inexpensive ways to tailor design to suit specific application needs. It is important to understand performance capabilities of new sensor designs through characterisation and optimisation of readout parameters. In this work three MAPSs were characterised. The first one - HEPAPS4 - designed for charged particle detection, with the potential technology application in the vertex detector for the International Linear Collider. The noise of the sensor was measured to be 35±5 e, which agrees well with simulated data. The dark current was found to be 175 pA/cm2. The SNR performance for minimum ionising particles detection was demonstrated to be 40. The sensor was also evaluated for indirect detection of thermal and fast neutrons using lithium and polyethylene converters. The technology performed well in such an application with an estimated fast neutron detection efficiency of ~0.01%. The second sensor characterised – Vanilla MAPS – was designed to evaluate new techniques for fast readout, small noise and reduced image lag. The system was capable to readout 150 full frames (520x520 pixels) per second; the sensor showed 14±4 e noise and decreased image lag. The dark current was found to be ~50 pA/cm2. The back-thinned version of the sensor demonstrated dramatic improvement in quantum efficiency from 0% to 20% at 220 nm. The third device is parametric sensor eLeNA. It features 14 test structure designed to evaluated noise reduction architectures. The most promising structures showed temporal noise values as low as 6 e and 20 e fixed pattern noise. Medipix as an example of the second class of imaging detectors - hybrid pixel detectors - was evaluated in two applications. It was used as the core element of the ATLAS radiation background monitoring system. The sensors were covered with neutron converters, which extended the number of radiation types that can be detected. X-ray calibration was performed, showing excellent tolerance of all 18 devices characterised. Detection efficiencies were estimated to be ~1% for thermal and ~0.1% for fast neutrons. The second application of Medipix was mass spectrometry. The detector was place in the focal plane of a prototype mass spectrometer. 2D representation of data allowed focusing correction of the ion beam. The system was capable to detect ions in the range of 5-25 keV. The detector characterisation with broad range of ions (from Cu to Pb) showed very good abundance agreement with table data

Performance evaluation of a fully depleted monolithic pixel detector chip in 150 nm CMOS technology

The depleted monolithic active pixel sensor (DMAPS) is a new concept integrating full CMOS circuitry onto a (fully) depletable silicon substrate wafer. The realization of prototypes of the DMAPS concept relies on the availability of multiple well CMOS processes and highly resistive substrates. The CMOS foundry ESPROS Photonics offers both and was chosen for prototyping. Two prototypes, EPCB01 and EPCB02, developed in a 150 nm process on a highly resistive n-type wafer of 50 µm thickness, were characterized. The prototypes have 352 square pixels of 40 µm pitch and a small n-well charge collection node with very low capacitance of 5 fF (n+-implantation size: 5 µm x 5 µm) and about 150 transistors per pixel (CSA and discriminator plus a small digital part). The characterization of the prototypes demonstrates the proof of principle of the concept. Prior to irradiation the prototypes show a signal from a minimum ionizing particle ranging from 2400 e- to 3000 e- while the noise is 30 e- due to the low capacitance. After the irradiation of the prototypes with neutrons up to a fluence of 5•1014 neutrons/cm2 the performance suffers from the radiation damage leading to a signal of 1000 e- and a higher noise of 60 e- due to the increase of the leakage current. The detection efficiency of the prototypes reduces from 94 % to 26 % after the fluence of 5•1014 particles/cm2. Due to the small fill factor the detection efficiency shows are strong dependence on the position within the pixel after irradiation. Thus the DMAPS concept with low fill factor can be used for precise vertex reconstruction in High Energy Physics experiments without severe performance loss up to moderate fluences (14 particles/cm2). The expected particle fluences inside of the volume of the upgrade of the ATLAS pixel detector exceed this limit. However, possible applications could be at future linear collider (ILC or CLIC) experiments and B-factories where the low material budget is of particular importance and the fluences are much less and X-ray imaging with low energy photons which would benefit from the good noise performance

A CMOS 90nm Digital Pixel Sensor Intended for a Visual Cortical Stimulator

RÉSUMÉ La capture d’images et le traitement d’images et de signaux font partie des domaines les plus en vogue de nos jours. Un autre domaine qui retient l’attention des chercheurs à travers le monde est celui qui regroupe les applications biomédicales - en particulier celles qui font le pont entre l’électronique et la biologie. L’équipe Polystim œuvre sur différents projets à la pointe de la technologie qui touchent à ces domaines, dont le projet Cortivision: un stimulateur visuel cortical. Le système englobe la capture et le traitement d’images ainsi que la stimulation du cortex pour donner une certaine perception d’images aux patients souffrant de cécité. Le but de ce travail est de concevoir le module de capture d’images de ce système. Les modes d’opération du capteur d’images doivent être configurables par l’usager. Il doit se distinguer par une gamme dynamique élevée, une consommation de puissance réduite, une haute vitesse d’acquisition, une surface réduite, la portabilité, la possibilité d’avoir du traitement d’images sur puce, et la facilité de l’intégrer dans un système sur puce avec le reste des modules de Cortivision. Un DPS (Digital Pixel Sensor) CMOS a été conçu et fabriqué avec la nouvelle technologie CMOS 90nm. Chaque pixel comprend une photodiode, un circuit de conversion de photocourant, un convertisseur analogique à numérique et une mémoire numérique de 8 bits, dans une surface de 9 µm x 9 µm avec un facteur de remplissage de 26% et 57 transistors. Le capteur offre plusieurs modes d’opération: • Un mode d’intégration linéaire. • Un mode logarithmique avec une gamme dynamique étendue qui permet d’accéder aux pixels indépendamment du temps mais avec une diminution de linéarité et un bruit plus prononcé. • Un mode différentiel qui soustrait deux images successives à même la puce pour obtenir une image binaire. Ce mode permet d’accélérer le traitement d’images et fonctionne à une vitesse plus élevée. Il peut être utilisé simultanément avec le mode linéaire ou avec le mode logarithmique. • Un mode d’expositions multiples qui est une option du mode linéaire pour augmenter la gamme dynamique, mais qui aurait l’effet de réduire la vitesse d’acquisition.----------ABSTRACT The image sensing and image processing fields make up some of the hottest topics in today’s industrial and research communities. Another field that is getting a lot of attention is biomedical applications - especially the combination of electronics to biology. The Polystim team is working on some state-of-the-art projects encompassing all that. One of these is the Cortivision project that consists of a visual cortical stimulator. The system comprises image sensing, image processing, and brain cortex stimulation to help blind patients acquire a sense of visual perception. The goal of this work is to cover the image sensing portion of the system. This requires the design and implementation of an image sensor which is user configurable to operate in several modes, has a high dynamic range, low power consumption, high frame rate capability, reduced surface area, is portable, allows some on-chip image processing, and can easily be integrated in a system-on-chip with the rest of the Cortivision modules. A CMOS Digital Pixel Sensor was designed and fabricated using the novel CMOS 90nm technology. Each pixel consists of a Photodiode, a photo-current conversion circuit, an Analog-to-Digital Converter and a digital 8-bit memory. It has a pixel pitch of 9µm with a Fill-Factor of 26% and 57 transistors. The sensor offers several modes of operation: • A linear integration mode. • A logarithmic mode that extends the dynamic range and allows time-independent pixel access at the cost of a forsaken linearity and an increase in noise. • A differential (or better termed difference) mode that allows subtracting two consecutive frames to obtain a binary image. This mode helps speed up the image processing and allows a very high frame rate. It can be used in conjunction with either the linear or the logarithmic modes of operation. • A multiple exposure mode that can be used in combination with the linear mode to increase the dynamic range at the expense of a decrease in frame rate

DESIGN OF A BURST MODE ULTRA HIGH-SPEED LOW-NOISE CMOS IMAGE SENSOR

Ultra-high-speed (UHS) image sensors are of interest for studying fast scientific phenomena and may also be useful in medicine. Several published studies have recently achieved frame rates of up to millions of frames per second (Mfps) using advanced processes and/or customized processes. This thesis presents a burst-mode (108 frames) UHS low-noise CMOS image sensor (CIS) based on charge-sweep transfer gates in an unmodified, standard 180 nm front-side-illuminated CIS process. By optimizing the photodiode geometry, the 52.8 μm pitch pixels with 20x20 μm^2 of active area, achieve a charge-transfer time of less than 10 ns. A proof-of-concept CIS was designed and fabricated. Through characterization, it is shown that the designed CIS has the potential to achieve 20 Mfps with an input-referred noise of 5.1 e− rms

Development of ASIC for SiPM sensor readout

L'abstract è presente nell'allegato / the abstract is in the attachmen