6,343 research outputs found

    Circulant and skew-circulant matrices as new normal-form realization of IIR digital filters

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    Normal-form fixed-point state-space realization of IIR (infinite-impulse response) filters are known to be free from both overflow oscillations and roundoff limit cycles, provided magnitude truncation arithmetic is used together with two's-complement overflow features. Two normal-form realizations are derived that utilize circulant and skew-circulant matrices as their state transition matrices. The advantage of these realizations is that the A-matrix has only N (rather than N2) distinct elements and is amenable to efficient memory-oriented implementation. The problem of scaling the internal signals in these structures is addressed, and it is shown that an approximate solution can be obtained through a numerical optimization method. Several numerical examples are included

    A study of digital techniques for signal processing Semiannual status report, 1 Feb. - 31 Jul. 1970

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    Adaptive array processing, dynamic programming, digital data transmission, recursive adaptive equalizers, and finite memory communication system

    The design and implementation of a microprocessor controlled adaptive filter

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    This thesis describes the construction and implementation of a microprocessor controlled recursive adaptive filter applied as a noise canceller. It describes the concept of the adaptive noise canceller, a method of estimating the received signal corrupted with additive interference (noise). This canceller has two inputs, the primary input containing the corrupted signal and the reference input consisting of the additive noise correlated in some unknown way to the primary noise. The reference input is filtered and subtracted from the primary input without degrading the desired components of the signal. This filtering process is adaptive and based on Widrow-Hoff Least-Mean-Square algorithm. Adaptive filters are programmable and have the capability to adjust their own parameters in situations where minimum piori knowledge is available about the inputs. For recursive filters, these parameters include feed-forward (non-recursive) as well as feedback (recursive) coefficients. A new design and implementation of the adaptive filter is suggested which uses a high speed 68000 microprocessor to accomplish the coefficients updating operation. Many practical problems arising in the hardware implementation are investigated. Simulation results illustrate the ability of the adaptive noise canceller to have an acceptable performance when the coefficients updating operation is carried out once every N sampling periods. Both simulation and hardware experimental results are in agreement

    Limit cycles in digital filters : a bibliography, 1975-1984

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    FINITE WORDLENGTH EFFECTS IN DIGITAL FILTERS

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    A survey of the state of the art and focused research in range systems, task 2

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    Many communication, control, and information processing subsystems are modeled by linear systems incorporating tapped delay lines (TDL). Such optimized subsystems result in full precision multiplications in the TDL. In order to reduce complexity and cost in a microprocessor implementation, these multiplications can be replaced by single-shift instructions which are equivalent to powers of two multiplications. Since, in general, the obvious operation of rounding the infinite precision TDL coefficients to the nearest powers of two usually yield quite poor system performance, the optimum powers of two coefficient solution was considered. Detailed explanations on the use of branch-and-bound algorithms for finding the optimum powers of two solutions are given. Specific demonstration of this methodology to the design of a linear data equalizer and its implementation in assembly language on a 8080 microprocessor with a 12 bit A/D converter are reported. This simple microprocessor implementation with optimized TDL coefficients achieves a system performance comparable to the optimum linear equalization with full precision multiplications for an input data rate of 300 baud. The philosophy demonstrated in this implementation is dully applicable to many other microprocessor controlled information processing systems

    Digital processing of signals in the presence of inter-symbol interference and additive noise

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