An Experimentally-Validated Verilog-A SPAD Model Extracted from TCAD Simulation

Single-photon avalanche diodes (SPAD) are photodetectors with exceptional characteristics. This paper proposes a new approach to model them in Verilog-A HDL with the help of a powerful tool: TCAD simulation. Besides, to the best of our knowledge, this is first model to incorporate a trap-assisted tunneling mechanism, a cross-section temperature dependence of the traps, and the self-heating effect. Comparison with experimental data establishes the validity of the model.Junta de Andalucía TIC 2012-2338Ministerio de Economía y Competitividad TEC2015-66878-C3-1-ROffice of Naval Research (USA) N00014141035

A CMOS 8×8 SPAD array for Time-of-Flight measurement and light-spot statistics

The design and simulation of a CMOS 8 × 8 single photon avalanche diode (SPAD) array is presented. The chip has been fabricated in a 0.18μm standard CMOS technology and implements a double functionality: measuring the Time-of-Flight with the help of a pulsed light source; or computing focal-plane statistics in biomedical imaging applications based on a concentrated light-spot. The incorporation of on-chip processing simplifies the interfacing of the array with the host system. The pixel pitch is 32μm, while the diameter of the quasi-circular active area of the SPADs is 12μm. The 113μm 2 active area is surrounded by a T-well guard ring. The resulting breakdown voltage is 10V with a maximum excess voltage of 1.8V. The pixel incorporates a novel active quenching/reset circuit. The array has been designed to operate with a laser pulsed at 20Mhz. The overall time resolution is 115ps. Focal-plane statistics are obtained in digital format. The maximum throughput of the digital output buffers is 200Mbps.Ministerio de Economía y Competitividad IPT-2011-1625- 430000, IPC-20111009Office of Naval Research (USA) N00014111031

Compact CMOS active quenching/recharge circuit for SPAD arrays

Avalanche diodes operating in Geiger mode are able to detect single photon events. They can be employed to photon counting and time-of-flight estimation. In order to ensure proper operation of these devices, the avalanche current must be rapidly quenched, and, later on, the initial equilibrium must be restored. In this paper, we present an active quenching/recharge circuit specially designed to be integrated in the form of an array of single-photon avalanche diode (SPAD) detectors. Active quenching and recharge provide benefits like an accurately controllable pulse width and afterpulsing reduction. In addition, this circuit yields one of the lowest reported area occupations and power consumptions. The quenching mechanism employed is based on a positive feedback loop that accelerates quenching right after sensing the avalanche current. We have employed a current starved inverter for the regulation of the hold-off time, which is more compact than other reported controllable delay implementations. This circuit has been fabricated in a standard 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology. The SPAD has a quasi-circular shape of 12 μm diameter active area. The fill factor is about 11%. The measured time resolution of the detector is 187 ps. The photon-detection efficiency (PDE) at 540 nm wavelength is about 5% at an excess voltage of 900 mV. The break-down voltage is 10.3 V. A dark count rate of 19 kHz is measured at room temperature. Worst case post-layout simulations show a 117 ps quenching and 280 ps restoring times. The dead time can be accurately tuned from 5 to 500 ns. The pulse-width jitter is below 1.8 ns when dead time is set to 40 ns.Ministerio de Economía y Competitividad TEC2012-38921-C02, IPT-2011-1625-430000, IPC-20111009 CDTIJunta de Andalucía TIC 2338-2013Office of Naval Research (USA) N00014141035

Timing measurements with silicon single photon avalanche diodes: principles and perspectives [Invited]

Picosecond timing of single photons has laid the foundation of a great variety of applications, from life sciences to quantum communication, thanks to the combination of ultimate sensitivity with a bandwidth that cannot be reached by analog recording techniques. Nowadays, more and more applications could still be enabled or advanced by progress in the available instrumentation, resulting in a steadily increasing research interest in this field. In this scenario, single-photon avalanche diodes (SPADs) have gained a key position, thanks to the remarkable precision they are able to provide, along with other key advantages like ruggedness, compactness, large signal amplitude, and room temperature operation, which neatly distinguish them from other solutions like superconducting nanowire single-photon detectors and silicon photomultipliers. With this work, we aim at filling a gap in the literature by providing a thorough discussion of the main design rules and tradeoffs for silicon SPADs and the electronics employed along them to achieve high timing precision. In the end, we conclude with our outlook on the future by summarizing new routes that could benefit from present and prospective timing features of silicon SPADs

Monolithic Perimeter Gated Single Photon Avalanche Diode Based Optical Detector in Standard CMOS

Since the 1930\u27s photomultiplier tubes (PMTs) have been used in single photon detection. Single photon avalanche diodes (SPADs) are p-n junctions operated in the Geiger mode. Unlike PMTs, CMOS based SPADs are smaller in size, insensitive to magnetic fields, less expensive, less temperature dependent, and have lower bias voltages. Using appropriate readout circuitry, they measure properties of single photons, such as energy, arrival time, and spatial path making them excellent candidates for single photon detection. CMOS SPADs suffer from premature breakdown due to the non-uniform distribution of the electric field. This prevents full volumetric breakdown of the device and reduces the detection effciency by increasing the noise. A novel device known as the perimeter gated SPAD (PGSPAD) is adopted in this dissertation for mitigating the premature perimeter breakdown without compromising the fill-factor of the device. The novel contributions of this work are as follows. A novel simulation model, including SPICE characteristics and the stochastic behavior, has been developed for the perimeter gated SPAD. This model has the ability to simulate the static current-voltage and dynamic response characteristics. It also simulates the noise and spectral response. A perimeter gated silicon photomultiplier, with improved signal to noise ratio, is reported for the first time. The gate voltage reduces the dark current of the silicon photomultiplier by preventing the premature breakdown. A digital SPAD with the tunable dynamic range and sensitivity is demonstrated for the first time. This pixel can be used for weak optical signal application when relatively higher sensitivity and lower input dynamic range is required. By making the sensitivity-dynamic range trade-off the same detector can be used for applications with relatively higher optical power. Finally, an array has been developed using the digital silicon photomultiplier in which the dead time of the pixels have been reduced. This digital photomultiplier features noise variation compensation between the pixels

Simulation study of resistor networks applied to an array of 256 SiPMs

[EN] In this work we describe a procedure to reduce the number of signals detected by an array of 256 Silicon Photo-multipliers (SiPMs) using a resistor network to divide the signal charge into few readout channels. Several configurations were modeled, and the pulsed signal at the readout contacts were simulated. These simulation results were experimentally tested on a specifically designed and manufactured set of printed circuit boards. Three network configurations were modeled. The modeling provided encouraging results for all three configurations. The measurements on the prototypes constructed for this study, however, provided useful position-sensitivity for only one of the network configurations. The lack of input signal amplification into the networks, the SiPM dark current, as well as the complexity of an eight layers board with parasitic capacitances, could have caused the degradation of resolving the impact photon position. This is hard to overcome with external printed circuit boards and components.This work was supported by the Spanish Plan Nacional de Investigación Científica, Desarrollo e Innovación Tecnológica (I+D+I) under Grant FIS2010-21216-CO2-01, the Valencian Local Government under Grant PROMETEO 2008/114 and through the JAE-Predoc grant from CSIC (BOE 29/01/2010).Gonzalez, A. J., Moreno, M., Barbera, J., Conde, P., Hernandez, L., Moliner, L., . . . Benlloch, J. M. (2013). Simulation study of resistor networks applied to an array of 256 SiPMs. IEEE Transactions on Nuclear Science, 60(2), 592-598. doi:10.1109/TNS.2012.2226051S59259860

SPICE Electrical Models and Simulations of Silicon Photomultipliers

We present and discuss a comprehensive electrical model for Silicon Photomultipliers (SiPMs) based on a microcell able to accurately simulate the avalanche current build-up and the self-quenching of its Single-Photon Avalanche Diode (SPAD) “pixel” with series-connected quenching resistor. The entire SiPM is modeled either as an array of microcells, each one individually triggered by independent incoming photons, or as two macrocells, one with microcells all firing concurrently while the other one with all quiescent microcells; the most suitable approach depends on the light excitation conditions and on the dimension (i.e. number of microcells) of the overall SiPM. We validated both models by studying the behavior of SiPMs in different operating conditions, in order to study the effect of photons pile-up, the deterministic and statistical mismatches between microcells, the impact of the number of firing microcells vs. the total one, and the role of different microcell parameters on the overall SiPM performance. The electrical models were developed in SPICE and can simulate both custom-process and CMOS-compatible SiPMs, with either vertical or horizontal current-flow. The proposed simulation tools can benefit both SiPM users, e.g. for designing the best readout electronics, and SiPM designers, for assessing the impact of each parameter on the overall detection performance and electrical behavior

Design and implementation of silicon single-photon avalanche photodiode modeling tool for QKD systems

Single-photon detection concept is the most crucial factor that determines the performance of quantum key distribution (QKD) systems. In this paper, a simulator with time domain visualizers and configurable parameters using continuous time simulation approach is presented for modeling and investigating the performance of single-photon detectors operating in Gieger mode at the wavelength of 830 nm. The widely used C30921S silicon avalanche photodiode was modeled in terms of avalanche pulse, the effect of experiment conditions such as excess voltage, temperature and average photon number on the photon detection efficiency, dark count rate and afterpulse probability. This work shows a general repeatable modeling process for significant performance evaluation. The most remarkable result emerged from the simulated data generated and detected by commercial devices is that the modeling process provides guidance for single-photon detectors design and characterization. The validation and testing results of the single-photon avalanche detectors (SPAD) simulator showed acceptable results with the theoretical and experimental results reported in related references and the device's data sheets

Technical Design Report for PANDA Electromagnetic Calorimeter (EMC)

This document presents the technical layout and the envisaged performance of the Electromagnetic Calorimeter (EMC) for the PANDA target spectrometer. The EMC has been designed to meet the physics goals of the PANDA experiment. The performance figures are based on extensive prototype tests and radiation hardness studies. The document shows that the EMC is ready for construction up to the front-end electronics interface