Validation by Measurements of a IC Modeling Approach for SiP Applications

The growing importance of signal integrity (SI) analysis in integrated circuits (ICs), revealed by modern systemin-package methods, is demanding for new models for the IC sub-systems which are both accurate, efficient and extractable by simple measurement procedures. This paper presents the contribution for the establishment of an integrated IC modeling approach whose performance is assessed by direct comparison with the signals measured in laboratory of two distinct memory IC devices. Based on the identification of the main blocks of a typical IC device, the modeling approach consists of a network of system-level sub-models, some of which with already demonstrated accuracy, which simulated the IC interfacing behavior. Emphasis is given to the procedures that were developed to validate by means of laboratory measurements (and not by comparison with circuit-level simulations) the model performance, which is a novel and important aspect that should be considered in the design of IC models that are useful for SI analysi

Modelação comportamental de dispostivos não-lineares (RF-digital) de entrada/saída

Doutoramento em Engenharia ElectrotécnicaEsta tese investiga a caracterização (e modelação) de dispositivos que realizam o interface entre os domínios digital e analógico, tal como os buffers de saída dos circuitos integrados (CI). Os terminais sem fios da atualidade estão a ser desenvolvidos tendo em vista o conceito de rádio-definido-por-software introduzido por Mitola. Idealmente esta arquitetura tira partido de poderosos processadores e estende a operação dos blocos digitais o mais próximo possível da antena. Neste sentido, não é de estranhar que haja uma crescente preocupação, no seio da comunidade científica, relativamente à caracterização dos blocos que fazem o interface entre os domínios analógico e digital, sendo os conversores digital-analógico e analógico-digital dois bons exemplos destes circuitos. Dentro dos circuitos digitais de alta velocidade, tais como as memórias Flash, um papel semelhante é desempenhado pelos buffers de saída. Estes realizam o interface entre o domínio digital (núcleo lógico) e o domínio analógico (encapsulamento dos CI e parasitas associados às linhas de transmissão), determinando a integridade do sinal transmitido. Por forma a acelerar a análise de integridade do sinal, aquando do projeto de um CI, é fundamental ter modelos que são simultaneamente eficientes (em termos computacionais) e precisos. Tipicamente a extração/validação dos modelos para buffers de saída é feita usando dados obtidos da simulação de um modelo detalhado (ao nível do transístor) ou a partir de resultados experimentais. A última abordagem não envolve problemas de propriedade intelectual; contudo é raramente mencionada na literatura referente à caracterização de buffers de saída. Neste sentido, esta tese de Doutoramento foca-se no desenvolvimento de uma nova configuração de medição para a caracterização e modelação de buffers de saída de alta velocidade, com a natural extensão aos dispositivos amplificadores comutados RF-CMOS. Tendo por base um procedimento experimental bem definido, um modelo estado-da-arte é extraído e validado. A configuração de medição desenvolvida aborda não apenas a integridade dos sinais de saída mas também do barramento de alimentação. Por forma a determinar a sensibilidade das quantias estimadas (tensão e corrente) aos erros presentes nas diversas variáveis associadas ao procedimento experimental, uma análise de incerteza é também apresentada.This thesis investigates the characterization (and modeling) of devices that perform the interface between the digital and analog domains, such as the output buffers of the Integrated Circuits (ICs). Modern wireless transceivers are moving towards the software-defined radio (SDR) concept proposed by Mitola. The ideal architecture makes use of powerful digital signal processors (DSP) and extends the digital blocks’s operation as close as possible to the antenna. In this way, it is not surprising that there is a growing concern regarding the characterization of the blocks that perform the interface between the analog and digital domains, being the analog-to-digital and digital-to-analog converters (ADCs/DACs) two good examples of these circuits. Within the high speed digital circuits, such as Flash memories, a similar role is played by the output buffers. They act as an interface between the digital (logic core) and the analog radio frequency domains (package/printed circuit board), determining the signal integrity of the transmitted data. In order to speed up the signal integrity analysis, at the design stage, it is fundamental to have models that are simultaneously computationally efficient and accurate. Typically, the extraction/validation of models for output buffers is performed by using characterization data obtained from either the simulation of the transistor level model (if available) or from measurements. The latter approach is not sensitive to intellectual property issues but is rarely addressed in literature referred to output buffers’ characterization. Therefore, this thesis addresses the development of a novel measurement setup for the characterization and modeling of high speed output buffers, naturally extendable to switched-mode RF-CMOS amplifiers. Based on a welldefined experimental procedure, a state of the art model is extracted and validated. The developed measurement setup addresses not only the integrity of the output signals (signal integrity) but also of the power supply voltages (power integrity). In order to determine the sensitivity of the estimated quantities (voltage and current) to the errors in the different variables of the experimental procedure, an uncertainty analysis is presented

Perioperative Neurocognitive Disorder: State of the Preclinical Science.

The purpose of this article is to provide a succinct summary of the different experimental approaches that have been used in preclinical postoperative cognitive dysfunction research, and an overview of the knowledge that has accrued. This is not intended to be a comprehensive review, but rather is intended to highlight how the many different approaches have contributed to our understanding of postoperative cognitive dysfunction, and to identify knowledge gaps to be filled by further research. The authors have organized this report by the level of experimental and systems complexity, starting with molecular and cellular approaches, then moving to intact invertebrates and vertebrate animal models. In addition, the authors' goal is to improve the quality and consistency of postoperative cognitive dysfunction and perioperative neurocognitive disorder research by promoting optimal study design, enhanced transparency, and "best practices" in experimental design and reporting to increase the likelihood of corroborating results. Thus, the authors conclude with general guidelines for designing, conducting and reporting perioperative neurocognitive disorder rodent research

Advanced information processing system: The Army fault tolerant architecture conceptual study. Volume 2: Army fault tolerant architecture design and analysis

Described here is the Army Fault Tolerant Architecture (AFTA) hardware architecture and components and the operating system. The architectural and operational theory of the AFTA Fault Tolerant Data Bus is discussed. The test and maintenance strategy developed for use in fielded AFTA installations is presented. An approach to be used in reducing the probability of AFTA failure due to common mode faults is described. Analytical models for AFTA performance, reliability, availability, life cycle cost, weight, power, and volume are developed. An approach is presented for using VHSIC Hardware Description Language (VHDL) to describe and design AFTA's developmental hardware. A plan is described for verifying and validating key AFTA concepts during the Dem/Val phase. Analytical models and partial mission requirements are used to generate AFTA configurations for the TF/TA/NOE and Ground Vehicle missions

Master of Science

thesisWildland firefighters are often called on to make tactical decisions under stressful conditions in order to suppress a fire. They frequently make these decisions based on their gained intuition over time, and also by considering previous specific fire experiences. This assists them in anticipating future fire behavior and developing tactics designed to suppress the fire while avoiding entrapment. These decisions can be hindered by human factors such as insufficient knowledge of surroundings and conditions, inexperience, overextension of resources, or loss of situational awareness. One potential tool for assisting fire managers in situations where human factors can hinder decision-making is the Wildland Urban Interface Evacuation (WUIVAC) model, which models minimum fire travel times to create geographic triggers for evacuation recommendations. Using a range of expected weather conditions and resource configurations, we generated a range of expected trigger buffer outcomes. Our objective was to use these outcomes to illustrate: (a) what spatial uncertainty is inherent in the geographic triggers produced by the range in expected conditions that contribute to fire behavior, and (b) after taking into account uncertainty, whether triggers are likely to be useful for rapid tactical decision-making. Utilizing 80 different tactical, weather, and fuel condition inputs, we demonstrated the use of WUIVAC for setting trigger points intended for use in planned firefighting operations to ensure entrapment avoidance. These triggers were used to determine when firefighting resources should disengage the fire and evacuate to a safety zone, shelter in place, turn down an assignment, or reengage and change tactics altogether based on predicted conditions. Using the 2007 Zaca Fire in the Los Padres National Forest, California as a case study, we show that WUIVAC can provide analytically driven physicallybased trigger points, and when coupled with intuitive decisions, it can assist in setting triggers for entrapment avoidance and ultimately contribute to firefighter safety

Otimização e melhoria da modulação comportamental para os interfaces de E/S analógica e de sinal misto de alta velocidade

Doutoramento em Engenharia ElectrotécnicaA integridade do sinal em sistemas digitais interligados de alta velocidade, e avaliada através da simulação de modelos físicos (de nível de transístor) é custosa de ponto vista computacional (por exemplo, em tempo de execução de CPU e armazenamento de memória), e exige a disponibilização de detalhes físicos da estrutura interna do dispositivo. Esse cenário aumenta o interesse pela alternativa de modelação comportamental que descreve as características de operação do equipamento a partir da observação dos sinais eléctrico de entrada/saída (E/S). Os interfaces de E/S em chips de memória, que mais contribuem em carga computacional, desempenham funções complexas e incluem, por isso, um elevado número de pinos. Particularmente, os buffers de saída são obrigados a distorcer os sinais devido à sua dinâmica e não linearidade. Portanto, constituem o ponto crítico nos de circuitos integrados (CI) para a garantia da transmissão confiável em comunicações digitais de alta velocidade. Neste trabalho de doutoramento, os efeitos dinâmicos não-lineares anteriormente negligenciados do buffer de saída são estudados e modulados de forma eficiente para reduzir a complexidade da modelação do tipo caixa-negra paramétrica, melhorando assim o modelo standard IBIS. Isto é conseguido seguindo a abordagem semi-física que combina as características de formulação do modelo caixa-negra, a análise dos sinais eléctricos observados na E/S e propriedades na estrutura física do buffer em condições de operação práticas. Esta abordagem leva a um processo de construção do modelo comportamental fisicamente inspirado que supera os problemas das abordagens anteriores, optimizando os recursos utilizados em diferentes etapas de geração do modelo (ou seja, caracterização, formulação, extracção e implementação) para simular o comportamento dinâmico não-linear do buffer. Em consequência, contributo mais significativo desta tese é o desenvolvimento de um novo modelo comportamental analógico de duas portas adequado à simulação em overclocking que reveste de um particular interesse nas mais recentes usos de interfaces de E/S para memória de elevadas taxas de transmissão. A eficácia e a precisão dos modelos comportamentais desenvolvidos e implementados são qualitativa e quantitativamente avaliados comparando os resultados numéricos de extracção das suas funções e de simulação transitória com o correspondente modelo de referência do estado-da-arte, IBIS.Signal integrity (SI) simulation of high-speed digital interconnected system via transistor level models is computational expensive (e.g. CPU time and memory storage), and requires the availability of physical details information of device’s internal structure. This scenario raises the interest for a behavioral modeling alternative which describes the device’s operation characteristics based on the observed input/output (I/O) electrical signal. I/O buffers that interface memory’s interconnects have major share in the computational load containing a very active complex functional part and high numbers of pins. Particularly, output buffers/drivers are forced to distort the I/O signals due to their nonlinear dynamics. In this concern, they constitute the integrated circuit (IC) bottleneck of ensuring reliable data transmission in the high-speed digital communication link. In this PhD work, the previously neglected driver’s nonlinear dynamic effects are efficiently captured to significantly reduce the state of the art black-box parametric modeling complexities and enhance the input/output buffers information specifications (IBIS). This is achieved by following the gray-box approach that merges the features of the black-box model’s formulation, the analysis of the observed I/O electrical signals and the buffer’s physical structure properties under practical operation conditions. This approach leads to physically inspired behavioral model’s construction procedure that overcomes the issues of the previous modeling approaches by optimizing the resources used at different model’s generation steps (i.e. characterization, formulation, extraction, and implementation) to mimic the driver’s nonlinear dynamic behavior. Moreover, the most important achievement is the development of a new two-port analog behavioral model for overclocking simulation that copes with the recent trends in I/O memory interfaces characterized by higher data rate transmission. The effectiveness and the accuracy of the developed and implemented behavioral models are qualitatively and quantitatively assessed by comparing the numerical results of their functions extraction and transient simulation to the ones simulated and extracted with transistor level models and the state of the art IBIS in order to validate their predictive and the generalization capabilities