Design techniques for wideband low-power Delta-Sigma analog-to-digital converters

Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations of a ΔΣ modulator. One is based on the discrete-time (DT) switched-capacitor (SC) circuitry and the other employs continuous-time (CT) circuitry. Compared to a CT structure, the DT ΔΣ ADC is easier to analyze and design, is more robust to process variations and jitter noise, and is more flexible in the multi-mode applications. On the other hand, the CT ΔΣ ADC does not suffer from the strict settling accuracy requirement for the loop filter and thus can achieve lower power dissipation and higher sampling frequency than its DT counterpart. In this thesis, both DT and CT ΔΣ ADCs are investigated. Several design innovations, in both system-level and circuit-level, are proposed to achieve lower power consumption and wider signal bandwidth. For DT ΔΣ ADCs, a new dynamic-biasing scheme is proposed to reduce opamp bias current and the associated signal-dependent harmonic distortion is minimized by using the low-distortion architecture. The technique was verified in a 2.5MHz BW and 13bit dynamic range DT ΔΣ ADC. In addition, a second-order noise coupling technique is presented to save two integrators for the loop filter, and to achieve low power dissipation. Also, a direct-charge-transfer (DCT) technique is suggested to reduce the speed requirements of the adder, which is also preferable in wideband low-power applications. For CT ΔΣ ADCs, a wideband low power CT 2-2 MASH has been designed. High linearity performance was achieved by using a modified low-distortion technique, and the modulator achieves higher noise-shaping ability than the single stage structure due to the inter-stage gain. Also, the quantization noise leakage due to analog circuit non-idealities can be adaptively compensated by a designed digital calibration filter. Using a 90nm process, simulation of the modulator predicts a 12bit resolution within 20MHz BW and consumes only 25mW for analog circuitry. In addition, the noise-coupling technique is investigated and proposed for the design of CT ΔΣ ADCs and it is promising to achieve low power dissipation for wideband applications. Finally, the application of noise-coupling technique is extended and introduced to high-accuracy incremental data converters. Low power dissipation can be expected

A 8 mW 72 dB Sigma Delta-modulator ADC with 2.4 MHz BW in 130 nm CMOS

A double-sampling sigma delta-ADC with bilinear integrators and a 7-level quantizer is presented. It achieves third order noise shaping with a second order modulator through quantization noise-coupling. The modulator is integrated in a 130 nm CMOS technology. For a clock frequency of 48 MHz and an oversampling ratio of 20 (2.4 MHz signal bandwidth), it achieves 72 dB DR and 68 dB SNR. The prototype consumes 8 mW from a 1.2 V voltage supply

Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits

This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ΣΔ) modulators (ΣΔMs) analog-todigital converters (ADCs). Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ΣΔM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 μW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB. The final prototype circuit is a highly area and power efficient ΣΔM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuit’s sensitivity to the circuit components’ variations. This continuous-time, 2-1 MASH ΣΔM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ΣΔM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the author’s knowledge the circuit achieves the lowest Walden FOMW for ΣΔMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date

Multi-stage noise shaping (MASH) delta-sigma modulators for wideband and multi-standard applications

Imperial Users onl

Efficient offline outer/inner DAC mismatch calibration in wideband ΔΣ ADCs

Distortion due to feedback DAC mismatch is a key limitation in Delta Sigma ADCs for wideband wireless communications. This article presents an efficient frequency-domain mask-based offline mismatch calibration method of both the outer DAC and the inner DACs in a Delta Sigma ADC. The test stimulus for the calibration is a two-tone signal near the band edge. To avoid the need for high-performance signal generation, a frequency mask is applied to void the stimulus signal and its phase noise. In this way, the method is robust against distortion and jitter in the stimulus signal, which therefore could be combined from two low-quality signal generators. The two-tone band-edge signal has the additional benefit that the number of needed samples of the excitation signal is very modest because as many intermodulations as possible contribute to the calculation of the mismatch errors of the DACs. Experimental results confirming the calibration method are obtained from a prototype chip, designed for an 85MHz signal bandwidth in 28nm CMOS technology. A two-tone stimulus around 78 MHz is applied to calculate the mismatch of the outer DAC and the inner DAC with only 68K samples. With the DACs calibrated, an SFDR improvement of 28.1 dB is achieved for a single-tone input at 5 MHz, while for a two-tone input around 71 MHz, the IM3 is improved from -63.6 dBc to below the noise floor (<-94.1 dBc). This illustrates the effectiveness of the approach

Flexible Sigma Delta Time-Interleaved Bandpass Analog-to-Digital Converter

Conversion of analog signals to their digital equivalent earlier in a circuit’s topology facilitates faster and more efficient exploitation of the information contained within. Analog-to-digital converters (ADCs) form the link between the analog and digital realms. In high frequency circuits ADCs must often be implemented further downstream after several stages of down-conversion, or through the use of more expensive technologies such as Bi-polar Junction Transistors or Gallium Arsenide. This thesis presents a technique to utilize Complimentary Metal Oxide Semiconductor technology in a parallel time-interleaved architecture. This will reduce circuit complexity and allow the ADC to be placed further upstream reducing the need for large and expensive analog hardware. This thesis utilizes an architecture that allows for higher frequency input signals through the use of down-sampling, parallel processing, and recombination. This thesis will also present the use of sigma delta based modulation in order to increase the resolution of the digital output signal. Exploitation of oversampling and the resultant noise-shaping characteristics of the sigma delta modulator will enable the user to gain resolution without the increased cost of implementing more expensive ADC architectures such as Flash. This thesis also presents a flexible converter such that both the center frequency and resolution can be modified by manipulating inputs. Specifically, the input and output filters as well as the sampling frequency can be tuned such that the circuit will operate at a particular center frequency. Also, the circuit will have flexible resolution which can be controlled by the clock input. Proof of concept is accomplished with a Matlab® simulation followed by schematic implementation in Cadence®. The design is constructed using IBM® 0.13 µm technology with a rail voltage of 1.2 V. Results are evaluated through the calculation of the effective number of bits and the signal to noise ratio. Conclusions and guidance on future research are provided

Multi-band Oversampled Noise Shaping Analog to Digital Conversion

Oversampled noise shaping analog to digital (A/D) converters, which are commonly known as delta-sigma (ΔΣ) converters, have the ability to convert relatively low bandwidth signals with very high resolution. Such converters achieve their high resolution by oversampling, as well as processing the signal and quantization noise with different transfer functions. The signal transfer function (STF) is typically a delay over the signal band while the noise transfer function (NTF) is designed to attenuate quantization noise in the signal band. A side effect of the NTF is an amplification of the noise outside the signal band. Thus, a digital filter subsequently attenuates the out-of-band quantization noise. The focus of this thesis is the investigation of ΔΣ architectures that increase the bandwidth where high resolution conversion can be achieved. It uses parallel architectures exploiting frequency or time slicing to meet this objective. Frequency slicing involves quantizing different portions of the signal frequency spectrum using several quantizers in parallel and then combining the results of the quantizers to form an overall result. Time slicing involves quantizing various groups of time domain signal samples with different quantizers in parallel and then combining the results of the quantizers to form an overall output. Several interesting observations can be made from this general perspective of frequency and time slicing. Although the representation of a signal are completely equivalent in time or frequency, the thesis shows that this is not the case for known frequency and time sliced A/D architectures. The performance of such systems under ideal conditions are compared for PCM as well as for ΔΣ A/D converters. A multi-band frequency sliced architecture for delta-sigma conversion is proposed and its performance is included in the above comparison. The architecture uses modulators which realize different NTFs for different portions of the signal band. Each band is converted in parallel. A bank of FIR filters attenuates the out of-band noise for each band and achieves perfect reconstruction of the signal component. A design procedure is provided for the design of the filter bank with reduced computational complexity. The use of complex NTFs in the multi-band ΔΣ architecture is also proposed. The peformance of real and complex NTFs is compared. Performance evaluations are made for ideal systems as well as systems suffering from circuit implementation imperfections such as finite opamp gain and mismatched capacitor ratios