Exploring Adaptive Implementation of On-Chip Networks

As technology geometries have shrunk to the deep submicron regime, the communication delay and power consumption of global interconnections in high performance Multi- Processor Systems-on-Chip (MPSoCs) are becoming a major bottleneck. The Network-on- Chip (NoC) architecture paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects and integration of large number of Processing Elements (PEs) on a chip. The choice of routing protocol and NoC structure can have a significant impact on performance and power consumption in on-chip networks. In addition, building a high performance, area and energy efficient on-chip network for multicore architectures requires a novel on-chip router allowing a larger network to be integrated on a single die with reduced power consumption. On top of that, network interfaces are employed to decouple computation resources from communication resources, to provide the synchronization between them, and to achieve backward compatibility with existing IP cores. Three adaptive routing algorithms are presented as a part of this thesis. The first presented routing protocol is a congestion-aware adaptive routing algorithm for 2D mesh NoCs which does not support multicast (one-to-many) traffic while the other two protocols are adaptive routing models supporting both unicast (one-to-one) and multicast traffic. A streamlined on-chip router architecture is also presented for avoiding congested areas in 2D mesh NoCs via employing efficient input and output selection. The output selection utilizes an adaptive routing algorithm based on the congestion condition of neighboring routers while the input selection allows packets to be serviced from each input port according to its congestion level. Moreover, in order to increase memory parallelism and bring compatibility with existing IP cores in network-based multiprocessor architectures, adaptive network interface architectures are presented to use multiple SDRAMs which can be accessed simultaneously. In addition, a smart memory controller is integrated in the adaptive network interface to improve the memory utilization and reduce both memory and network latencies. Three Dimensional Integrated Circuits (3D ICs) have been emerging as a viable candidate to achieve better performance and package density as compared to traditional 2D ICs. In addition, combining the benefits of 3D IC and NoC schemes provides a significant performance gain for 3D architectures. In recent years, inter-layer communication across multiple stacked layers (vertical channel) has attracted a lot of interest. In this thesis, a novel adaptive pipeline bus structure is proposed for inter-layer communication to improve the performance by reducing the delay and complexity of traditional bus arbitration. In addition, two mesh-based topologies for 3D architectures are also introduced to mitigate the inter-layer footprint and power dissipation on each layer with a small performance penalty.Siirretty Doriast

Best-first heuristic search for multicore machines

To harness modern multicore processors, it is imperative to develop parallel versions of fundamental algorithms. In this paper, we compare different approaches to parallel best-first search in a shared-memory setting. We present a new method, PBNF, that uses abstraction to partition the state space and to detect duplicate states without requiring frequent locking. PBNF allows speculative expansions when necessary to keep threads busy. We identify and fix potential livelock conditions in our approach, proving its correctness using temporal logic. Our approach is general, allowing it to extend easily to suboptimal and anytime heuristic search. In an empirical comparison on STRIPS planning, grid pathfinding, and sliding tile puzzle problems using 8-core machines, we show that A*, weighted A* and Anytime weighted A* implemented using PBNF yield faster search than improved versions of previous parallel search proposals

Ethernet Networks for Real-Time Use in the ATLAS Experiment

Ethernet became today's de-facto standard technology for local area networks. Defined by the IEEE 802.3 and 802.1 working groups, the Ethernet standards cover technologies deployed at the first two layers of the OSI protocol stack. The architecture of modern Ethernet networks is based on switches. The switches are devices usually built using a store-and-forward concept. At the highest level, they can be seen as a collection of queues and mathematically modelled by means of queuing theory. However, the traffic profiles on modern Ethernet networks are rather different from those assumed in classical queuing theory. The standard recommendations for evaluating the performance of network devices define the values that should be measured but do not specify a way of reconciling these values with the internal architecture of the switches. The introduction of the 10 Gigabit Ethernet standard provided a direct gateway from the LAN to the WAN by the means of the WAN PHY. Certain aspects related to the actual use of WAN PHY technology were vaguely defined by the standard. The ATLAS experiment at CERN is scheduled to start operation at CERN in 2007. The communication infrastructure of the Trigger and Data Acquisition System will be built using Ethernet networks. The real-time operational needs impose a requirement for predictable performance on the network part. In view of the diversity of the architectures of Ethernet devices, testing and modelling is required in order to make sure the full system will operate predictably. This thesis focuses on the testing part of the problem and addresses issues in determining the performance for both LAN and WAN connections. The problem of reconciling results from measurements to architectural details of the switches will also be tackled. We developed a scalable traffic generator system based on commercial-off-the-shelf Gigabit Ethernet network interface cards. The generator was able to transmit traffic at the nominal Gigabit Ethernet line rate for all frame sizes specified in the Ethernet standard. The calculation of latency was performed with accuracy in the range of +/- 200 ns. We indicate how certain features of switch architectures may be identified through accurate throughput and latency values measured for specific traffic distributions. At this stage, we present a detailed analysis of Ethernet broadcast support in modern switches. We use a similar hands-on approach to address the problem of extending Ethernet networks over long distances. Based on the 1 Gbit/s traffic generator used in the LAN, we develop a methodology to characterise point-to-point connections over long distance networks. At higher speeds, a combination of commercial traffic generators and high-end servers is employed to determine the performance of the connection. We demonstrate that the new 10 Gigabit Ethernet technology can interoperate with the installed base of SONET/SDH equipment through a series of experiments on point-to-point circuits deployed over long-distance network infrastructure in a multi-operator domain. In this process, we provide a holistic view of the end-to-end performance of 10 Gigabit Ethernet WAN PHY connections through a sequence of measurements starting at the physical transmission layer and continuing up to the transport layer of the OSI protocol stack

Strategy-based dynamic assignment in transit networks with passenger queues

This thesis develops a mathematical framework to solve the problem of dynamic assignment in densely connected public transport (or transit – the two words are interchangeably used) networks where users do not time their arrival at a stop with the lines’ timetable (if any is published). In the literature there is a fairly broad agreement that, in such transport systems, passengers would not select the single best itinerary available, but would choose a travel strategy, namely a bundle of partially overlapping itineraries diverging at stops along different lines. Then, they would follow a specific path depending on what line arrives first at the stop. From a graph-theory point of view, this route-choice behaviour is modelled as the search for the shortest hyperpath (namely an acyclic sub-graph which includes partially overlapping single paths) to the destination in the hypergraph that describes the transit network. In this thesis, the hyperpath paradigm is extended to model route choice in a dynamic context, where users might be prevented from boarding the lines of their choice because of capacity constraints. More specifically, if the supplied capacity is insufficient to accommodate the travel demand, it is assumed that passenger congestion leads to the formation of passenger First In, First Out (FIFO) queues at stops and that, in the context of commuting trips, passengers have a good estimate of the expected number of vehicle passages of the same line that they must let go before being able to board. By embedding the proposed demand model in a fully dynamic assignment model for transit networks, this thesis also fills in the gap currently existing in the realm of strategy-based transit assignment, where – so far – models that employ the FIFO queuing mechanism have proved to be very complex, and a theoretical framework for reproducing the dynamic build-up and dissipation of queues is still missing.Open Acces

Smart charging strategies for electric vehicle charging stations

Although the concept of transportation electrification holds enormous prospects in addressing the global environmental pollution problem, consumer concerns over the limited availability of charging stations and long charging/waiting times are major contributors to the slow uptake of plug-in electric vehicles (PEVs) in many countries. To address the consumer concerns, many countries have undertaken projects to deploy a network of both fast and slow charging stations, commonly known as electric vehicle charging networks. While a large electric vehicle charging network will certainly be helpful in addressing PEV owners\u27 concerns, the full potential of this network cannot be realised without the implementation of smart charging strategies. For example, the charging load distribution in an EV charging network would be expected to be skewed towards stations located in hotspot areas, instigating longer queues and waiting times in these areas, particularly during afternoon peak traffic hours. This can also lead to a major challenge for the utilities in the form of an extended PEV charging load period, which could overlap with residential evening peak load hours, increasing peak demand and causing serious issues including network instability and power outages. This thesis presents a smart charging strategy for EV charging networks. The proposed smart charging strategy finds the optimum charging station for a PEV owner to ensure minimum charging time, travel time and charging cost. The problem is modelled as a multi-objective optimisation problem. A metaheuristic solution in the form of ant colony optimisation (ACO) is applied to solve the problem. Considering the influence of pricing on PEV owners\u27 behaviour, the smart charging strategy is then extended to address the charging load imbalance problem in the EV network. A coordinated dynamic pricing model is presented to reduce the load imbalance, which contributes to a reduction in overlaps between residential and charging loads. A constraint optimization problem is formulated and a heuristic solution is introduced to minimize the overlap between the PEV and residential peak load periods. In the last part of this thesis, a smart management strategy for portable charging stations (PCSs) is introduced. It is shown that when smartly managed, PCSs can play an important role in the reduction of waiting times in an EV charging network. A new strategy is proposed for dispatching/allocating PCSs during various hours of the day to reduce waiting times at public charging stations. This also helps to decrease the overlap between the total PEV demand and peak residential load

Exploration and Design of Power-Efficient Networked Many-Core Systems

Multiprocessing is a promising solution to meet the requirements of near future applications. To get full benefit from parallel processing, a manycore system needs efficient, on-chip communication architecture. Networkon- Chip (NoC) is a general purpose communication concept that offers highthroughput, reduced power consumption, and keeps complexity in check by a regular composition of basic building blocks. This thesis presents power efficient communication approaches for networked many-core systems. We address a range of issues being important for designing power-efficient manycore systems at two different levels: the network-level and the router-level. From the network-level point of view, exploiting state-of-the-art concepts such as Globally Asynchronous Locally Synchronous (GALS), Voltage/ Frequency Island (VFI), and 3D Networks-on-Chip approaches may be a solution to the excessive power consumption demanded by today’s and future many-core systems. To this end, a low-cost 3D NoC architecture, based on high-speed GALS-based vertical channels, is proposed to mitigate high peak temperatures, power densities, and area footprints of vertical interconnects in 3D ICs. To further exploit the beneficial feature of a negligible inter-layer distance of 3D ICs, we propose a novel hybridization scheme for inter-layer communication. In addition, an efficient adaptive routing algorithm is presented which enables congestion-aware and reliable communication for the hybridized NoC architecture. An integrated monitoring and management platform on top of this architecture is also developed in order to implement more scalable power optimization techniques. From the router-level perspective, four design styles for implementing power-efficient reconfigurable interfaces in VFI-based NoC systems are proposed. To enhance the utilization of virtual channel buffers and to manage their power consumption, a partial virtual channel sharing method for NoC routers is devised and implemented. Extensive experiments with synthetic and real benchmarks show significant power savings and mitigated hotspots with similar performance compared to latest NoC architectures. The thesis concludes that careful codesigned elements from different network levels enable considerable power savings for many-core systems.Siirretty Doriast

Optimal Configuration of Extreme Fast Charging Stations Integrated with Energy Storage System and Photovoltaic Panels in Distribution Networks

Extreme fast charging (XFC) for electric vehicles (EVs) has emerged recently because of the short charging period. However, the extreme high charging power of EVs at XFC stations may severely impact distribution networks. This paper addresses the estimation of the charging power demand of XFC stations and the design of multiple XFC stations with renewable energy resources in current distribution networks. First, a Monte Carlo (MC) simulation tool was created utilizing the EV arrival time and state-of-charge (SOC) distributions obtained from the dataset of vehicle travel surveys. Various impact factors are considered to obtain a realistic estimation of the charging power demand of XFC stations. Then, a method for determining the optimal energy capacity of the energy storage system (ESS), ESS rated power, and size of photovoltaic (PV) panels for multiple XFC stations in a distribution network is presented, with the goal of achieving an optimal configuration. The optimal power flow technique is applied to this optimization so that the optimal solutions meet not only the charging demand but also the operational constraints related to XFC, ESS, PV panels, and distribution networks. Simulation results of a use case indicate that the presented MC simulation can estimate approximate real-world XFC charging demand, and the optimized ESS and PV units in multiple XFC stations in the distribution network can reduce the annual total cost of XFC stations and improve the performance of the distribution network