A two-level approach to automated conformance testing of VHDL designs

For manufacturers of consumer electronics, conformance testing of embedded software is a vital issue. To improve performance, parts of this software are implemented in hardware, often designed in the Hardware Description Language VHDL. Conformance testing is a time consuming and error-prone process. Thus automating (parts of) this process is essential. There are many tools for test generation and for VHDL simulation. However, most test generation tools operate on a high level of abstraction and applying the generated tests to a VHDL design is a complicated task. For each specific case one can build a layer of dedicated circuitry and/or software that performs this task. It appears that the ad-hoc nature of this layer forms the bottleneck of the testing process. We propose a {em generic solution for bridging this gap: a generic layer of software dedicated to interface with VHDL implementations. It consists of a number of Von Neumann-like components that can be instantiated for each specific VHDL design. This paper reports on the construction of and some initial experiences with a concrete tool environment based on these principles

Hardware/Software Co-design of Communication Protocols

An important aspect in providing high performance distributed systems such as multimedia systems is the combined use of hardware and software in the end systems. System design techniques should allow hardware/software co-design to integrate both means of implementation. In this paper, we show how the standardized formal language Estelle can be used to facilitate co-design. The system will first be designed in Estelle. At the point in time of final decision on which parts to implement in software and which in hardware, the original specification will be split into several partial specifications. The software parts are translated into C code, while the hardware parts are translated into VHDL code for further analysis and development. We present a tool environment which supports the protocol developer in the design and implementation process. A simple Video-on-Demand example shows the usefulness of the tool environment

The DS-Pnet modeling formalism for cyber-physical system development

This work presents the DS-Pnet modeling formalism (Dataflow, Signals and Petri nets), designed for the development of cyber-physical systems, combining the characteristics of Petri nets and dataflows to support the modeling of mixed systems containing both reactive parts and data processing operations. Inheriting the features of the parent IOPT Petri net class, including an external interface composed of input and output signals and events, the addition of dataflow operations brings enhanced modeling capabilities to specify mathematical data transformations and graphically express the dependencies between signals. Data-centric systems, that do not require reactive controllers, are designed using pure dataflow models. Component based model composition enables reusing existing components, create libraries of previously tested components and hierarchically decompose complex systems into smaller sub-systems. A precise execution semantics was defined, considering the relationship between dataflow and Petri net nodes, providing an abstraction to define the interface between reactive controllers and input and output signals, including analog sensors and actuators. The new formalism is supported by the IOPT-Flow Web based tool framework, offering tools to design and edit models, simulate model execution on the Web browser, plus model-checking and software/hardware automatic code generation tools to implement controllers running on embedded devices (C,VHDL and JavaScript). A new communication protocol was created to permit the automatic implementation of distributed cyber-physical systems composed of networks of remote components communicating over the Internet. The editor tool connects directly to remote embedded devices running DS-Pnet models and may import remote components into new models, contributing to simplify the creation of distributed cyber-physical applications, where the communication between distributed components is specified just by drawing arcs. Several application examples were designed to validate the proposed formalism and the associated framework, ranging from hardware solutions, industrial applications to distributed software applications

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

Advanced information processing system: The Army fault tolerant architecture conceptual study. Volume 1: Army fault tolerant architecture overview

Digital computing systems needed for Army programs such as the Computer-Aided Low Altitude Helicopter Flight Program and the Armored Systems Modernization (ASM) vehicles may be characterized by high computational throughput and input/output bandwidth, hard real-time response, high reliability and availability, and maintainability, testability, and producibility requirements. In addition, such a system should be affordable to produce, procure, maintain, and upgrade. To address these needs, the Army Fault Tolerant Architecture (AFTA) is being designed and constructed under a three-year program comprised of a conceptual study, detailed design and fabrication, and demonstration and validation phases. Described here are the results of the conceptual study phase of the AFTA development. Given here is an introduction to the AFTA program, its objectives, and key elements of its technical approach. A format is designed for representing mission requirements in a manner suitable for first order AFTA sizing and analysis, followed by a discussion of the current state of mission requirements acquisition for the targeted Army missions. An overview is given of AFTA's architectural theory of operation

Wearable Platform for Automatic Recognition of Parkinson Disease by Muscular Implication Monitoring

The need for diagnostic tools for the characterization of progressive movement disorders - as the Parkinson Disease (PD) - aiming to early detect and monitor the pathology is getting more and more impelling. The parallel request of wearable and wireless solutions, for the real-time monitoring in a non-controlled environment, has led to the implementation of a Quantitative Gait Analysis platform for the extraction of muscular implications features in ordinary motor action, such as gait. The here proposed platform is used for the quantification of PD symptoms. Addressing the wearable trend, the proposed architecture is able to define the real-time modulation of the muscular indexes by using 8 EMG wireless nodes positioned on lower limbs. The implemented system “translates” the acquisition in a 1-bit signal, exploiting a dynamic thresholding algorithm. The resulting 1-bit signals are used both to define muscular indexes both to drastically reduce the amount of data to be analyzed, preserving at the same time the muscular information. The overall architecture has been fully implemented on Altera Cyclone V FPGA. The system has been tested on 4 subjects: 2 affected by PD and 2 healthy subjects (control group). The experimental results highlight the validity of the proposed solution in Disease recognition and the outcomes match the clinical literature results

A Design Methodology for Space-Time Adapter

This paper presents a solution to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. By explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs a C description of Input/Output data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a Resource Constraints Graph (RCG). The RCG properties enable an efficient architecture space exploration in order to synthesize a STAR component. The proposed approach has been tested to design an industrial data mixing block example: an Ultra-Wideband interleaver.Comment: ISBN : 978-1-59593-606-