Power Reductions with Energy Recovery Using Resonant Topologies

The problem of power densities in system-on-chips (SoCs) and processors has become more exacerbated recently, resulting in high cooling costs and reliability issues. One of the largest components of power consumption is the low skew clock distribution network (CDN), driving large load capacitance. This can consume as much as 70% of the total dynamic power that is lost as heat, needing elaborate sensing and cooling mechanisms. To mitigate this, resonant clocking has been utilized in several applications over the past decade. An improved energy recovering reconfigurable generalized series resonance (GSR) solution with all the critical support circuitry is developed in this work. This LC resonant clock driver is shown to save about 50% driver power (\u3e40% overall), on a 22nm process node and has 50% less skew than a non-resonant driver at 2GHz. It can operate down to 0.2GHz to support other energy savings techniques like dynamic voltage and frequency scaling (DVFS). As an example, GSR can be configured for the simpler pulse series resonance (PSR) operation to enable further power saving for double data rate (DDR) applications, by using de-skewing latches instead of flip-flop banks. A PSR based subsystem for 40% savings in clocking power with 40% driver active area reduction xii is demonstrated. This new resonant driver generates tracking pulses at each transition of clock for dual edge operation across DVFS. PSR clocking is designed to drive explicit-pulsed latches with negative setup time. Simulations using 45nm IBM/PTM device and interconnect technology models, clocking 1024 flip-flops show the reductions, compared to non-resonant clocking. DVFS range from 2GHz/1.3V to 200MHz/0.5V is obtained. The PSR frequency is set \u3e3× the clock rate, needing only 1/10th the inductance of prior-art LC resonance schemes. The skew reductions are achieved without needing to increase the interconnect widths owing to negative set-up times. Applications in data circuits are shown as well with a 90nm example. Parallel resonant and split-driver non-resonant configurations as well are derived from GSR. Tradeoffs in timing performance versus power, based on theoretical analysis, are compared for the first time and verified. This enables synthesis of an optimal topology for a given application from the GSR

Development of limb volume measuring system

The mechanisms underlying the reductions in orthostatic tolerance associated with weightlessness are not well established. Contradictory results from measurements of leg volume changes suggest that altered venomotor tone and reduced blood flow may not be the only contributors to orthostatic intolerance. It is felt that a more accurate limb volume system which is insensitive to environmental factors will aid in better quantification of the hemodynamics of the leg. Of the varous limb volume techniques presently available, the ultrasonic limb volume system has proven to be the best choice. The system as described herein is free from environmental effects, safe, simple to operate and causes negligible radio frequency interference problems. The segmental ultrasonic ultrasonic plethysmograph is expected to provide a better measurement of limb volume change since it is based on cross-sectional area measurements

Multi-stage noise shaping (MASH) delta-sigma modulators for wideband and multi-standard applications

Imperial Users onl

Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

A Low-Power, Reconfigurable, Pipelined ADC with Automatic Adaptation for Implantable Bioimpedance Applications

Biomedical monitoring systems that observe various physiological parameters or electrochemical reactions typically cannot expect signals with fixed amplitude or frequency as signal properties can vary greatly even among similar biosignals. Furthermore, advancements in biomedical research have resulted in more elaborate biosignal monitoring schemes which allow the continuous acquisition of important patient information. Conventional ADCs with a fixed resolution and sampling rate are not able to adapt to signals with a wide range of variation. As a result, reconfigurable analog-to-digital converters (ADC) have become increasingly more attractive for implantable biosensor systems. These converters are able to change their operable resolution, sampling rate, or both in order convert changing signals with increased power efficiency. Traditionally, biomedical sensing applications were limited to low frequencies. Therefore, much of the research on ADCs for biomedical applications focused on minimizing power consumption with smaller bias currents resulting in low sampling rates. However, recently bioimpedance monitoring has become more popular because of its healthcare possibilities. Bioimpedance monitoring involves injecting an AC current into a biosample and measuring the corresponding voltage drop. The frequency of the injected current greatly affects the amplitude and phase of the voltage drop as biological tissue is comprised of resistive and capacitive elements. For this reason, a full spectrum of measurements from 100 Hz to 10-100 MHz is required to gain a full understanding of the impedance. For this type of implantable biomedical application, the typical low power, low sampling rate analog-to-digital converter is insufficient. A different optimization of power and performance must be achieved. Since SAR ADC power consumption scales heavily with sampling rate, the converters that sample fast enough to be attractive for bioimpedance monitoring do not have a figure-of-merit that is comparable to the slower converters. Therefore, an auto-adapting, reconfigurable pipelined analog-to-digital converter is proposed. The converter can operate with either 8 or 10 bits of resolution and with a sampling rate of 0.1 or 20 MS/s. Additionally, the resolution and sampling rate are automatically determined by the converter itself based on the input signal. This way, power efficiency is increased for input signals of varying frequency and amplitude

New Cdc Design Tool For Analog Layout Workflow

The placement and routing on CMOS analog layout design had always been a time consuming and irritating process due to large amount of transistor devices placements, arrangements and a lot of critical nets routing constraint. Manual efforts to complete analog layout design took few weeks to months’ time in previous project cycle according to the complexity of the circuit. In the meantime, designer needs to convert the devices from schematic into layout in canvas of layout editor, and then arrange the devices accordingly one by one or group by group by moving the devices in order to complete device placement. While for routing, even though there are different auto-routers in existing layout editing tool, but these routers are mostly developed for digital design and unable to route analog signals precisely especially when there are constraints for the routing like matching and shielding. This research presents a new automation solution, Cartoon Diagram Compiler (CDC) tool that enabling a significant productivity improvement on analog layout design. The automation tool provides capability to drag-and-drop the transistor devices/instance cells from schematics canvas to floor planning canvas and is able to auto-place non-critical cells and devices in a virtual mode before converting into real layout. After the floorplan/placement fulfill the design requirement, topologies generator can be used for quick preview of routing option and auto-router support for constrained (shield critical net) and un-constrained nets routing. The area and routing quality nearly matched with hand-drawn layout. The CDC tool has been compare and evaluated on Intel in-house analog layout design projects. In research evaluation, the average time to complete manual device placement and layout routing required 640 minutes and 554 minutes respectively. With device placement and layout routing process only required 139 minutes and 112 minutes or significant reduction in period of about 5.14x and 6.31x respectively. In conclusion, CDC tool increases the productivity by allowing fully automatic derivation of placement and routing, incremental design updates and smart placement guaranteeing design rule free from violation

EMC Performance Evaluation of Various PCB Designs through Simulation and Measurements

The applied research presented in this thesis is intended to deepen the understanding of various concepts related to PCB design with respect to EMC and RF performance. The first topic addressed is embedded capacitance of a PCB. The work includes decoupling capacitors and their placement relative to the IC in a combination of three different PCB stack-ups. The evaluation is performed in the frequency domain and time domain. The next topic discussed is the EMC/ EMI filters which are essential measurements to protect a device or subsystem from EMI. The circuit\u27s load is usually unknown. A generic filter design is built, which allows the placement of various PCB structures to evaluate filters under different load and source impedance. To convert voltage effciently, SMPS buck converters are widely used. To suppress EMI, various counter measures for differential mode, and common mode are discussed and measured with a conducted emission (CE) voltage method (V) to evaluate their performance. The designed snubber is evaluated in the time domain by measuring the ringing and the suppressed target frequency content. The results of the above four topics are utilized in a VHF auto tuner design. The results of the embedded capacitance frequency domain evaluation show that the two evaluated 6-layer designs outperform the 4-layer design. Additionally, the 6-layer design with far spaced power plane outperforms the 6-layer version 3 design with not-far spaced power plane referenced to the top signal layer. Grouped capacitors outperform the not grouped capacitors. For not grouped capacitors on a 6-layer design, the evaluation in time and frequency domain shows that the 6-layer designs are particularly enhancing higher frequency content suppression regardless if the capacitors are grouped or not. The filter evaluation showed that for a 2nd order filter the capacitor placed close to the high impedance side shows increased performance. The 3rd order structures π and T show that there is no significant performance decrease if the filter is mounted one way or another. The correlation of the measured and simulated data showed that the ideal case simulations are valid for the ideal behavior of the filter. Due to the bandwidth of a π filter, large components with lower self-resonance frequencies are favorable. In real-world applications, a π is favorable because there never is just an LC or CL structure due to bulk or decoupling capacitors. The SMPS evaluation showed that the snubber could be designed with Adamczyk\u27s and Spence\u27s approach. The tested EMC filter structures showed clearly that a single component shows an impact on the CE (V) measurement and can be identified by its self-resonant frequency. The filter can be designed for different target frequency ranges, and depending on the design, it will show better or worse results. The shield was added, and the measured interference dropped mainly to the ambient level. On the VHF auto tuner each evaluated topic is discussed and shows that around 50% of the used components are related to EMC. The presented work illustrates the multidisciplinary character of electromagnetic compatibility (EMC)