Performance Evaluation of Evolutionary Algorithms for Analog Integrated Circuit Design Optimisation

An automated sizing approach for analog circuits using evolutionary algorithms is presented in this paper. A targeted search of the search space has been implemented using a particle generation function and a repair-bounds function that has resulted in faster convergence to the optimal solution. The algorithms are tuned and modified to converge to a better optimal solution with less standard deviation for multiple runs compared to standard versions. Modified versions of the artificial bee colony optimisation algorithm, genetic algorithm, grey wolf optimisation algorithm, and particle swarm optimisation algorithm are tested and compared for the optimal sizing of two operational amplifier topologies. An extensive performance evaluation of all the modified algorithms showed that the modifications have resulted in consistent performance with improved convergence for all the algorithms. The implementation of parallel computation in the algorithms has reduced run time. Among the considered algorithms, the modified artificial bee colony optimisation algorithm gave the most optimal solution with consistent results across multiple runs

Multi-objective Digital VLSI Design Optimisation

Modern VLSI design's complexity and density has been exponentially increasing over the past 50 years and recently reached a stage within its development, allowing heterogeneous, many-core systems and numerous functions to be integrated into a tiny silicon die. These advancements have revealed intrinsic physical limits of process technologies in advanced silicon technology nodes. Designers and EDA vendors have to handle these challenges which may otherwise result in inferior design quality, even failures, and lower design yields under time-to-market pressure. Multiple or many design objectives and constraints are emerging during the design process and often need to be dealt with simultaneously. Multi-objective evolutionary algorithms show flexible capabilities in maintaining multiple variable components and factors in uncertain environments. The VLSI design process involves a large number of available parameters both from designs and EDA tools. This provides many potential optimisation avenues where evolutionary algorithms can excel. This PhD work investigates the application of evolutionary techniques for digital VLSI design optimisation. Automated multi-objective optimisation frameworks, compatible with industrial design flows and foundry technologies, are proposed to improve solution performance, expand feasible design space, and handle complex physical floorplan constraints through tuning designs at gate-level. Methodologies for enriching standard cell libraries regarding drive strength are also introduced to cooperate with multi-objective optimisation frameworks, e.g., subsequent hill-climbing, providing a richer pool of solutions optimised for different trade-offs. The experiments of this thesis demonstrate that multi-objective evolutionary algorithms, derived from biological inspirations, can assist the digital VLSI design process, in an industrial design context, to more efficiently search for well-balanced trade-off solutions as well as optimised design space coverage. The expanded drive granularity of standard cells can push the performance of silicon technologies with offering improved solutions regarding critical objectives. The achieved optimisation results can better deliver trade-off solutions regarding power, performance and area metrics than using standard EDA tools alone. This has been not only shown for a single circuit solution but also covered the entire standard-tool-produced design space

System level performance and yield optimisation for analogue integrated circuits

Advances in silicon technology over the last decade have led to increased integration of analogue and digital functional blocks onto the same single chip. In such a mixed signal environment, the analogue circuits must use the same process technology as their digital neighbours. With reducing transistor sizes, the impact of process variations on analogue design has become prominent and can lead to circuit performance falling below specification and hence reducing the yield.This thesis explores the methodology and algorithms for an analogue integrated circuit automation tool that optimizes performance and yield. The trade-offs between performance and yield are analysed using a combination of an evolutionary algorithm and Monte Carlo simulation. Through the integration of yield parameter into the optimisation process, the trade off between the performance functions can be better treated that able to produce a higher yield. The results obtained from the performance and variation exploration are modelled behaviourally using a Verilog-A language. The model has been verified with transistor level simulation and a silicon prototype.For a large analogue system, the circuit is commonly broken down into its constituent sub-blocks, a process known as hierarchical design. The use of hierarchical-based design and optimisation simplifies the design task and accelerates the design flow by encouraging design reuse.A new approach for system level yield optimisation using a hierarchical-based design is proposed and developed. The approach combines Multi-Objective Bottom Up (MUBU) modelling technique to model the circuit performance and variation and Top Down Constraint Design (TDCD) technique for the complete system level design. The proposed method has been used to design a 7th order low pass filter and a charge pump phase locked loop system. The results have been verified with transistor level simulations and suggest that an accurate system level performance and yield prediction can be achieved with the proposed methodology

Automated Placement Of A Transistor Pair For Analogue

The performances of analogue circuits are affected by surrounding parameters such as levels of noise, thermal gradients of a circuit, and parasitic effects from both resistive and capacitive part. As there are no effective approaches to handle these analogue constraints as mentioned above, the focuses to develop IC design tools are bended towards digital circuits. The purpose of this research is to introduce a complete methodology for transistor pair placement for analogue layout using a concept of cells and arrays based on migration and reuse. The entire process consists of Standard Cell Generation to produce standard cell for analogue circuits, Matching Generator with array alignment to generate transistor matching of common-centroid arrangement, and Auto Routing for global routing. The methodology is translated into automation by a graphical user interface to render a fully functional layout designs in a few steps and fraction of time. This research describes such a system in obtaining a layout that can be configured like a set of building blocks that meets all design specifications. In comparison to all the different approaches that have been discussed and analysed prior to this research, a new design flow for analogue layout combined with automation is constructed by considering transistor matching as a constraint

Variation-aware behavioural modelling using support vector machines and affine arithmetic

AGIAS Generalised Interval Arithmetic Simulator (AGIAS) is a specialised simulator which uses affine arithmetic to model parameter variations. It uses a specialised root-finding algorithm to simulate analogue circuits with parameter variations in one single simulation run. This is a significant speed-up compared to the multiple runs needed by industrialised solutions such as Monte-Carlo (MC) or Worst-Case Analysis (WCA). Currently, AGIAS can simulate analogue circuits only under very specific conditions. In many cases, circuits can only be simulated for certain operating points. If the circuits is to be evaluated in other operating points, the solver becomes numerically unstable and simulation fails. In these cases, interval widths approach infinity. Behavioural modelling of analogue circuits was introduced by researchers working around limitations of simulators. Most early approaches require expert knowledge and insight into the circuit which is modelled. In recent years, Machine Learning techniques for automatic generation of behavioural models have made their way into the field. This thesis combines Machine Learning techniques with affine arithmetic to include the effects of parameter variations into models. Support Vector Machines (SVMs) train two sets of parameters: one slope parameter and one offset parameter. These parameters are replaced by affine forms. Using these two parameters allows affine SVMs to model effects of parameter variations with varying widths. Training requires additional information about maximum and minimum values in addition to the nominal values in the data set. Based on these changes, affine ε Support Vector Machine (ε̂SVR) and ν Support Vector Machine (ν̂SVR) algorithms for regression are presented. To train the affine parameters directly and profit from the Sequential Minimal Optimisation algorithm (SMO)’s selectivity, the SMO is extended to handle the new, larger optimisation problems. The new affine SVMs are tested on analogue circuits that have been chosen based on whether they could be simulated with AGIAS and how strongly non-linear their characteristic function is