AUTOMATED SYNTHESIS OF VIRTUALBLOCKS FOR INTERFACING SYSTEM UNDER TEST

In this thesis, I/O signal recognizers, called VIRTUALBLOCKS, are synthesized to interface with a SYSTEM UNDER TEST (SUT). Methods for automated synthesis of virtualblocks allow us to simulate environment interfaces with SUT and also perform fault detection on SUT. Such methods must be able to recognize incoming sequences of signals from SUT, and upon the signal recognition determine the proper outgoing sequences of signals to SUT. We characterize our systems into four distinctive systems: system under test, AUXILIARY SYSTEM, controller and external environment. The auxiliary system is represented as a form of condition system Petri net (virtualblocks) and interacts with SUT along with the interaction among the controller and the external environment. Fault detection is performed by subsystems called DETECTBLOCKS synthesized from the virtualblocks. We present construction procedures for virtualblocks andamp; detectblocks and discuss the notion of LEGALITY and DETECTABILITY. Finally, we illustrate our approach using a model of a scanner control unit

Design of a Control System for a Reconfigurable Engine Assembly Line

Today’s automotive manufacturing environment is dynamic. It is characterized by short life cycles of products especially in powertrain, due in part to changing Government regulations for fuel economy. In the USA, the National Highway Traffic and Safety Administration (NHTSA), Corporate Average Fuel Economy (CAFE) mandates an average of 29 miles per gallon (mpg), gradually increasing to 35.5 mpg by 2016 and 54.5 mpg towards 2025. Life cycles of engines and transmissions have consequently shortened, driving automakers to develop and manufacture more efficient powertrains. Not long ago, plants produced engines for decades, with minor modifications warranting slight manufacturing line rework. Conversely, today’s changing trends require machines and complete engine line overhauls rendering initial setups obsolete. Automakers compete to satisfy government regulations for best mileage and also lower manufacturing cost, thus the adoption of Reconfigurable Manufacturing Systems (RMS). Production lines follow modularity in designs, for hardware and software, to adapt to new business conditions, economically and time-wise. Information Technology (IT) and Controls are growing closer with the line of demarcation disappearing in manufacturing. Controls are benefiting from opportunities in IT, hardware and software. The advent of agent-based technology which are autonomous, cooperative and extendible in different production activities, helped to develop controls for RMS in academia. Component-based software suitable for RMS modularity and plug-and-play hardware/software components has gained decades of popularity in the software industry. This thesis implements distributed controls imbedding component-based technology and IEC 61311-3 function block standard for automotive engine assembly, which will contribute to these developments. The control architecture provides reconfigurability which is lacking in current manufacturing systems. The research imbeds: 1- Reconfigurability - Fitting RMS-designed hardware towards new manufacturing, 2- Reusability - Building software library for reuse across assembly lines, and 3- Plug-and-Play - Embedding easy to assemble software components (function blocks)

HIERARCHICAL HYBRID-MODEL BASED DESIGN, VERIFICATION, SIMULATION, AND SYNTHESIS OF MISSION CONTROL FOR AUTONOMOUS UNDERWATER VEHICLES

The objective of modeling, verification, and synthesis of hierarchical hybrid mission control for underwater vehicle is to (i) propose a hierarchical architecture for mission control for an autonomous system, (ii) develop extended hybrid state machine models for the mission control, (iii) use these models to verify for logical correctness, (iv) check the feasibility of a simulation software to model the mission executed by an autonomous underwater vehicle (AUV) (v) perform synthesis of high-level mission coordinators for coordinating lower-level mission controllers in accordance with the given mission, and (vi) suggest further design changes for improvement. The dissertation describes a hierarchical architecture in which mission level controllers based on hybrid systems theory have been, and are being developed using a hybrid systems design tool that allows graphical design, iterative redesign, and code generation for rapid deployment onto the target platform. The goal is to support current and future autonomous underwater vehicle (AUV) programs to meet evolving requirements and capabilities. While the tool facilitates rapid redesign and deployment, it is crucial to include safety and performance verification into each step of the (re)design process. To this end, the modeling of the hierarchical hybrid mission controller is formalized to facilitate the use of available tools and newly developed methods for formal verification of safety and performance specifications. A hierarchical hybrid architecture for mission control of autonomous systems with application to AUVs is proposed and a theoretical framework for the models that make up the architecture is outlined. An underwater vehicle like any other autonomous system is a hybrid system, as the dynamics of the vehicle as well as its vehicle level control is continuous whereas the mission level control is discrete, making the overall system a hybrid system i.e., one possessing both continuous and discrete states. The hybrid state machine models of the mission controller modules is derived from their implementation done using TEJA, a software for representing hybrid systems with support for auto code generation. The verification of their logical correctness properties has been done using UPPAAL, a software tool for verification of timed automata a special kind of hybrid system. A Teja to Uppaal converter, called dem2xml, has been created at Applied Reserarch Lab that converts a hybrid (timed) autonomous system description in Teja to an Uppaal system description. Verification work involved developing abstract models for the lower level vehicle controllers with which the mission controller modules interact and follow a hierarchical approach: Assuming the correctness of level-zero or vehicle controllers, we establish the correctness of level-one mission controller modules, and then the correctness of level-two modules, etc. The goal of verification is to show that any valid meaning for a mission formalized in our research verifies the safe and correct execution of actions. Simulation of the sequence of actions executed for each of the operations give a better view of the combined working of the mission coordinators and the low level controllers. So we next looked into the feasibility of simulating the operations executed during a mission. A Perl program has been developed to convert the UPPAAL files in .xml format to OpenGL graphic files. The graphic files simulate the steps involved in the execution of a sequence of operations executed by an AUV. The highest level coordinators send mission orders to be executed by the lower level controllers. So a more generalized design of the highest level controllers would help to incorporate the execution of a variety of missions for a vast field of applications. Initially, we consider manually synthesized mission coordinator modules. Later we design automated synthesis of coordinators. This method synthesizes mission coordinators which coordinate the lower level controllers for the execution of the missions ordered and can be used for any autonomous system

Deterministic Generation of Regular Languages in Discrete Event Systems

[ES] En este artículo se propone una red de Petri, interpretada, estocástica, (st-IPN), como modelo para representar el lenguaje regular obtenido a partir de la combinación de señales de entrada - salida, en un sistema de eventos discretos (SED) en lazo cerrado. Las señales de entrada, son las señales externas que afecten al sistema y las órdenes de control emitidas por el controlador a la planta y las señales de salida son las respuestas de los sensores a las órdenes de control. La st-IPN propuesta, es un generador determinista del lenguaje legal de sistema, capaz de representar secuencias de eventos temporizados de naturaleza estocástica. El modelo propuesto puede ser aplicado a sistemas de gran escala, a partir de la división del sistema en subsistemas, ya que el modelo global puede ser encontrado con base en la composición de los modelos de los subsistemas.[EN] In this paper is proposed a stochastic interpreted Petri net, (st-IPN) as a model to represent the regular language derived from the combination of input signals in a Discrete Event System (DES) in closed loop. The input signals are external signals affecting the system and the control commands issued by the controller to the plant and the output signals are the responses of the sensors to the control commands. The st-IPN proposed is a deterministic generator of the system legal language able to represent sequences of stochastic timed events. The proposed model can be applied to large-scale systems, from the division of the system into subsystems, since the global model can be a composition of the subsystems models.Este trabajo ha sido realizado parcialmente gracias a la comisión académica financiada por la Universidad del Cauca, referencia 2.3-31.2/05 2011.Muñoz, DM.; Correcher Salvador, A.; García Moreno, E.; Morant Anglada, FJ. (2016). Generación Determinística de Lenguajes Legales para Sistemas de Eventos Discretos. Revista Iberoamericana de Automática e Informática industrial. 13(2):207-219. https://doi.org/10.1016/j.riai.2016.01.002OJS207219132Ashley, J., & Holloway, L. E. (2004). Qualitative Diagnosis of Condition Systems. Discrete Event Dynamic Systems, 14(4), 395-412. doi:10.1023/b:disc.0000039787.51382.afBasile, F., Chiacchio, P., Coppola, J., De Tommasi, G., june 2011. Identification of petri nets using timing information. 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