8,747 research outputs found
From FPGA to ASIC: A RISC-V processor experience
This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC
AER-based robotic closed-loop control system
Address-Event-Representation (AER) is an
asynchronous protocol for transferring the information of
spiking neuro-inspired systems. Actually AER systems are able
to see, to ear, to process information, and to learn. Regarding to
the actuation step, the AER has been used for implementing
Central Pattern Generator algorithms, but not for controlling
the actuators in a closed-loop spike-based way. In this paper we
analyze an AER based model for a real-time neuro-inspired
closed-loop control system. We demonstrate it into a differential
control system for a two-wheel vehicle using feedback AER
information. PFM modulation has been used to power the DC
motors of the vehicle and translation into AER of encoder
information is also presented for the close-loop. A codesign
platform (called AER-Robot), based into a Xilinx Spartan 3
FPGA and an 8051 USB microcontroller, with power stages for
four DC motors has been used for the demonstrator.Junta de Andalucía P06-TIC-01417Ministerio de Educación y Ciencia TEC2006-11730-C03-0
Telemetry downlink interfaces and level-zero processing
The technical areas being investigated are as follows: (1) processing of space to ground data frames; (2) parallel architecture performance studies; and (3) parallel programming techniques. Additionally, the University administrative details and the technical liaison between New Mexico State University and Goddard Space Flight Center are addressed
Prompt Application-Transparent Transaction Revalidation in Software Transactional Memory
Software Transactional Memory (STM) allows encapsulating shared-data accesses within transactions, executed with atomicity and isolation guarantees. The assessment of the consistency of a running transaction is performed by the STM layer at specific points of its execution, such as when a read or write access to a shared object occurs, or upon a commit attempt. However, performance and energy efficiency issues may arise when no shared-data read/write operation occurs for a while along a thread running a transaction. In this scenario, the STM layer may not regain control for a considerable amount of time, thus not being able to early detect if such transaction has become inconsistent in the meantime. To tackle this problem we present an STM architecture that, thanks to a lightweight operating system support, is able to perform a fine-grain periodic (hence prompt) revalidation of running transactions. Our proposal targets Linux and x86 systems and has been integrated with the open source TinySTM package. Experimental results with a port of the TPC-C benchmark to STM environments show the effectiveness of our solution
A Score-Driven Conditional Correlation Model for Noisy and Asynchronous Data: an Application to High-Frequency Covariance Dynamics
The analysis of the intraday dynamics of correlations among high-frequency
returns is challenging due to the presence of asynchronous trading and market
microstructure noise. Both effects may lead to significant data reduction and
may severely underestimate correlations if traditional methods for
low-frequency data are employed. We propose to model intraday log-prices
through a multivariate local-level model with score-driven covariance matrices
and to treat asynchronicity as a missing value problem. The main advantages of
this approach are: (i) all available data are used when filtering correlations,
(ii) market microstructure noise is taken into account, (iii) estimation is
performed through standard maximum likelihood methods. Our empirical analysis,
performed on 1-second NYSE data, shows that opening hours are dominated by
idiosyncratic risk and that a market factor progressively emerges in the second
part of the day. The method can be used as a nowcasting tool for high-frequency
data, allowing to study the real-time response of covariances to macro-news
announcements and to build intraday portfolios with very short optimization
horizons.Comment: 30 pages, 10 figures, 7 table
Programmability and Performance of Parallel ECS-based Simulation of Multi-Agent Exploration Models
While the traditional objective of parallel/distributed simulation techniques has been mainly in improving performance and making very large models tractable, more recent research trends targeted complementary aspects, such as the “ease of programming”. Along this line, a recent proposal called Event and Cross State (ECS) synchronization, stands as a solution allowing to break the traditional programming rules proper of Parallel Discrete Event Simulation (PDES) systems, where the application code processing a specific event is only allowed to access the state (namely the memory image) of the target simulation object. In fact with ECS, the programmer is allowed to write ANSI-C event-handlers capable of accessing (in either read or write mode) the state of whichever simulation object included in the simulation model. Correct concurrent execution of events, e.g., on top of multi-core machines, is guaranteed by ECS with no intervention by the programmer, who is in practice exposed to a sequential-style programming model where events are processed one at a time, and have the ability to access the current memory image of the whole simulation model, namely the collection of the states of any involved object. This can strongly simplify the development of specific models, e.g., by avoiding the need for passing state information across concurrent objects in the form of events. In this article we investigate on both programmability and performance aspects related to developing/supporting a multi-agent exploration model on top of the ROOT-Sim PDES platform, which supports ECS
Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition
A neuromorphic chip that combines CMOS analog spiking neurons and memristive
synapses offers a promising solution to brain-inspired computing, as it can
provide massive neural network parallelism and density. Previous hybrid analog
CMOS-memristor approaches required extensive CMOS circuitry for training, and
thus eliminated most of the density advantages gained by the adoption of
memristor synapses. Further, they used different waveforms for pre and
post-synaptic spikes that added undesirable circuit overhead. Here we describe
a hardware architecture that can feature a large number of memristor synapses
to learn real-world patterns. We present a versatile CMOS neuron that combines
integrate-and-fire behavior, drives passive memristors and implements
competitive learning in a compact circuit module, and enables in-situ
plasticity in the memristor synapses. We demonstrate handwritten-digits
recognition using the proposed architecture using transistor-level circuit
simulations. As the described neuromorphic architecture is homogeneous, it
realizes a fundamental building block for large-scale energy-efficient
brain-inspired silicon chips that could lead to next-generation cognitive
computing.Comment: This is a preprint of an article accepted for publication in IEEE
Journal on Emerging and Selected Topics in Circuits and Systems, vol 5, no.
2, June 201
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