An Asynchronous Circuit Design Language (ACDL)

This correspondence describes a special purpose Asynchronous Circuit Design Language (ACDL) for specifying the terminal behavior of asynchronous sequential circuits. The language is a valuable tool for formalizing and documenting asynchronous designs, as well as providing a user interface to a completely automated synthesis system. The language includes many special features which permit quick and precise specification of terminal behavior and is best suited for problems that are currently being described informally by word statements. Copyright © 1974 by The Institute of Electrical and Electronics Engineers, Inc

An asynchronous circuit design language system

This paper presents a system for specifying the behavior of asynchronous sequential circuits. The system consists of a special purpose Asynchronous Circuit Design Language (ACDL), a translator and a flow table generation algorithm. The language includes many special features which permit quick and precise specification of terminal behavior. It is best suited for problems originating from a word description of the circuit\u27s operation. The translator is written with the XPL Translator Writing System and is a syntax-directed compilation method. From the translated ACDL specifications, the flow table algorithm generates a primitive flow table which is the required input for the conventional synthesis procedures of asynchronous sequential circuits. A thorough description of the translator and flow table programs is given in the Appendices. In addition a number of example problems illustrating the use of ACDL are provided --Abstract, page ii

Ultra-Low Power and Radiation Hardened Asynchronous Circuit Design

This dissertation proposes an ultra-low power design methodology called bit-wise MTNCL for bit-wise pipelined asynchronous circuits, which combines multi-threshold CMOS (MTCMOS) with bit-wise pipelined NULL Convention Logic (NCL) systems. It provides the leakage power advantages of an all high-Vt implementation with a reasonable speed penalty compared to the all low-Vt implementation, and has negligible area overhead. It was enhanced to handle indeterminate standby states. The original MTNCL concept was enhanced significantly by sleeping Registers and Completion Logic as well as Combinational circuits to reduce area, leakage power, and energy per operation. This dissertation also develops an architecture that allows NCL circuits to recover from a Single Event Upset (SEU) or Single Event Latchup (SEL) fault without any data loss. Finally, an accurate throughput derivation formula for pipelined NCL circuits was developed, which can be used for static timing analysis

SOFT ERROR IN ASYNCHRONOUS CIRCUIT DESIGN

Soft error considers as a serious concern in state holders as it can cause the circuit to malfunction temporarily. Soft errors are categorised as Single Event Upset (SEU) and Single Event Transient (SET). Radiation actuate soft errors are often happen to most of the electronic products especially with the CMOS technology development. A particle striking on any of the electronic products that can produce soft errors that can be either single event upset or single event transient. Soft errors are not reproducible, and it corrupt the data integrity of the system. This project presents several nodes that are injected with the soft error in the asynchronous circuit. An asynchronous circuit was design using the dual rail encoding and 3-6 code converter while the soft error is represented by using XOR logic gate. The effect of the soft error to the asynchronous circuit is it changed the stored data and it produce errors on the waveform which mean the output parameters are not the same as output parameters. In the project, the presence and absence of error are analysed by observing the output parameter of the waveform that are produced. The software is used to design entry, synthesize the design, compile the schematic diagram, stimulate the gate level schematic of the asynchronous circuit as well as the addition of soft error in the circuit. Moreover, logic gates are commonly used to design the C-element in the software used. The software used to complete the project is Quartus ii Prime Lite edition software

Automation In The Design Of Asynchronous Sequential Circuits

Sequential switching circuits are commonly classified as being either synchronous or asynchronous. Clock pulses synchronize the operations of the synchronous circuit. The operation of an asynchronous circuit is usually assumed to be independent of such clocks. The operating speed of an asynchronous circuit is thus limited only by basic device speed. One disadvantage of asynchronous circuit design has been the complexity of the synthesis procedures for large circuits

High Temperature CMOS Silicon Carbide Asynchronous Circuit Design

Designing a digital circuit to operate in an extreme temperature range is a challenge with increasing demand for a solution. Large variations in temperature have a distinct impact on electron mobilities causing substantial changes to the threshold voltage of the devices. These physical changes affect the setup and hold times of clocked components, such as D-Flip Flops, of a traditional synchronous digital circuit. Focusing primarily on high temperature circuit operation, this dissertation presents a digital circuit design methodology pairing an asynchronous circuit design paradigm called NULL Convention Logic (NCL) as well as traditional Boolean circuitry with a wide-bandgap semiconductor material, Silicon Carbide (SiC). A total of nineteen circuits have been designed and fabricated. Chip testing results show correct operation for all circuits returned from fabrication, with most performing at or above the targeted temperature of 300°C

Comparison of Various Pipelined and Non-Pipelined SCl 8051 ALUs

This paper describes the development of an 8-bit SCL 8051 ALU with two versions: SCL 8051 ALU with nsleep and sleep signals and SCL 8051 ALU without nsleep. Both versions have combinational logic (C/L), registers, and completion components, which all utilize slept gates. Both three-stage pipelined and non-pipelined designs were examined for both versions. The four designs were compared in terms of area, speed, leakage power, average power and energy per operation. The SCL 8051 ALU without nsleep is smaller and faster, but it has greater leakage power. It also has lower average power, and less energy consumption than the SCL 8051 ALU with both nsleep and sleep signals. The pipelined SCL 8051 ALU is bigger, slower, and has larger leakage power, average power and energy consumption than the non-pipelined SCL 8051 ALU

Ultra-low power multi-threshold asynchronous circuit design

A multi-threshold null convention logic circuit is described. The circuit includes a first circuit, a first high-threshold transistor coupled to Vcc, and an inverter receiving power from the first high-threshold transistor, driven by the first circuit, and including an output