16,907 research outputs found
A micropower centroiding vision processor
Published versio
Excitability in autonomous Boolean networks
We demonstrate theoretically and experimentally that excitable systems can be
built with autonomous Boolean networks. Their experimental implementation is
realized with asynchronous logic gates on a reconfigurabe chip. When these
excitable systems are assembled into time-delay networks, their dynamics
display nanosecond time-scale spike synchronization patterns that are
controllable in period and phase.Comment: 6 pages, 5 figures, accepted in Europhysics Letters
(epljournal.edpsciences.org
Quantum Dot Cellular Automata Check Node Implementation for LDPC Decoders
The quantum dot Cellular Automata (QCA) is an emerging nanotechnology that has gained significant research interest in recent years. Extremely small feature sizes, ultralow power consumption, and high clock frequency make QCA a potentially attractive solution for implementing computing architectures at the nanoscale. To be considered as a suitable CMOS substitute, the QCA technology must be able to implement complex real-time applications with affordable complexity. Low density parity check (LDPC) decoding is one of such applications. The core of LDPC decoding lies in the check node (CN) processing element which executes actual decoding algorithm and contributes toward overall performance and complexity of the LDPC decoder. This study presents a novel QCA architecture for partial parallel, layered LDPC check node. The CN executes Normalized Min Sum decoding algorithm and is flexible to support CN degree dc up to 20. The CN is constructed using a VHDL behavioral model of QCA elementary circuits which provides a hierarchical bottom up approach to evaluate the logical behavior, area, and power dissipation of the whole design. Performance evaluations are reported for the two main implementations of QCA i.e. molecular and magneti
Towards a bio-inspired mixed-signal retinal processor
Published versio
Metastability-Containing Circuits
In digital circuits, metastability can cause deteriorated signals that
neither are logical 0 or logical 1, breaking the abstraction of Boolean logic.
Unfortunately, any way of reading a signal from an unsynchronized clock domain
or performing an analog-to-digital conversion incurs the risk of a metastable
upset; no digital circuit can deterministically avoid, resolve, or detect
metastability (Marino, 1981). Synchronizers, the only traditional
countermeasure, exponentially decrease the odds of maintained metastability
over time. Trading synchronization delay for an increased probability to
resolve metastability to logical 0 or 1, they do not guarantee success.
We propose a fundamentally different approach: It is possible to contain
metastability by fine-grained logical masking so that it cannot infect the
entire circuit. This technique guarantees a limited degree of metastability
in---and uncertainty about---the output.
At the heart of our approach lies a time- and value-discrete model for
metastability in synchronous clocked digital circuits. Metastability is
propagated in a worst-case fashion, allowing to derive deterministic
guarantees, without and unlike synchronizers. The proposed model permits
positive results and passes the test of reproducing Marino's impossibility
results. We fully classify which functions can be computed by circuits with
standard registers. Regarding masking registers, we show that they become
computationally strictly more powerful with each clock cycle, resulting in a
non-trivial hierarchy of computable functions
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