Detection and robustness of digital image watermarking signals : a communication theory approach

The detection and robustness of the watermark signal is studied from a communications point of view. The contributions of this dissertation are presented in two parts. The first part, which covers the detection aspect, introduces a new digital image watermarking approach that embeds meaningful information in a copyright protection watermark signal; demonstrates the need to approach the watermark signal as a power-constrained signal; studies the relationship between the watermark signal dimension and the image capacity to the signal; explains the similarities and differences between detecting the watermark signal and detecting a signal over a spread-spectrum communication channel; and analyzes the application of sequence detection techniques (MAPSD and MLSD) to the watermark signal. The second part, which covers the robustness aspect, introduces a novel multidimensional interleaving algorithm that increases the signal\u27s robustness against burst errors; presents, analyzes, and compares two techniques for implementing the algorithm (a sliding window technique and a successive partitioning technique); and demonstrates the increase in watermark signal robustness as a result of applying this multidimensional interleaving. This increase of the signal\u27s robustness is shown in the 2-D case by applying the 2-D version of the interleaving algorithm to watermark signals embedded in still images (where the signal layout is in 2-D), and in the 3-D case by applying the 3-D version of the interleaving algorithm to watermark signals embedded in video sequences (where the signal layout is in 3-D)

High-Performance Energy-Efficient and Reliable Design of Spin-Transfer Torque Magnetic Memory

In this dissertation new computing paradigms, architectures and design philosophy are proposed and evaluated for adopting the STT-MRAM technology as highly reliable, energy efficient and fast memory. For this purpose, a novel cross-layer framework from the cell-level all the way up to the system- and application-level has been developed. In these framework, the reliability issues are modeled accurately with appropriate fault models at different abstraction levels in order to analyze the overall failure rates of the entire memory and its Mean Time To Failure (MTTF) along with considering the temperature and process variation effects. Design-time, compile-time and run-time solutions have been provided to address the challenges associated with STT-MRAM. The effectiveness of the proposed solutions is demonstrated in extensive experiments that show significant improvements in comparison to state-of-the-art solutions, i.e. lower-power, higher-performance and more reliable STT-MRAM design

ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY

With the rapid growth in consumer electronics, people expect thin, smart and powerful devices, e.g. Google Glass and other wearable devices. However, as portable electronic products become smaller, energy consumption becomes an issue that limits the development of portable systems due to battery lifetime. In general, simply reducing device size cannot fully address the energy issue. To tackle this problem, we propose an on-chip interconnect infrastructure and pro- gram storage structure for a coarse-grained reconfigurable architecture (CGRA) with emerging non-volatile embedded memory (MRAM). The interconnect is composed of a matrix of time-multiplexed switchboxes which can be dynamically reconfigured with the goal of energy reduction. The number of processors performing computation can also be adapted. The use of MRAM provides access to high-density storage and lower memory energy consumption versus more standard SRAM technologies. The combination of CGRA, MRAM, and flexible on-chip interconnection is considered for signal processing. This application domain is of interest based on its time-varying computing demands. To evaluate CGRA architectural features, prototype architectures have been pro- totyped in a field-programmable gate array (FPGA). Measurements of energy, power, instruction count, and execution time performance are considered for a scalable num- ber of processors. Applications such as adaptive Viterbi decoding and Reed Solomon coding are used for evaluation. To complete this thesis, a time-scheduled switchbox was integrated into our CGRA model. This model was prototyped on an FPGA. It is shown that energy consumption can be reduced by about 30% if dynamic design reconfiguration is performed

Study and simulation of low rate video coding schemes

The semiannual report is included. Topics covered include communication, information science, data compression, remote sensing, color mapped images, robust coding scheme for packet video, recursively indexed differential pulse code modulation, image compression technique for use on token ring networks, and joint source/channel coder design