Approximation Algorithms for Network Design Problems

We consider different variants of network design problems. Given a set of points in the plane we search for a shortest interconnection of them. In this general formulation the problem is known as Steiner tree problem. We consider the special case of octilinear Steiner trees in the presence of hard and soft obstacles. In an octilinear Steiner tree the line segments connecting the points are allowed to run either in horizontal, vertical or diagonal direction. An obstacle is a connected region in the plane bounded by a simple polygon. No line segment of an octilinear Steiner tree is allowed to lie in the interior of a hard obstacle. If we intersect a Steiner tree with the interior of a soft obstacle, no connected component of the induced subtree is allowed to be longer than a given fixed length. We provide polynomial time approximation schemes for the octilinear Steiner tree problem in the presence of hard and soft obstacles. These were the first presented approximation schemes introduced for the problems. Additionally, we introduce a (2+epsilon)-approximation algorithm for soft obstacles. We then turn to Euclidean group Steiner trees. Instead of a set of fixed points we get for each point a set of potential locations (combined into groups) and we need to pick only one location of each group. The groups we consider lie inside disjoint regions fulfilling a special property so-called alpha-fatness. Roughly speaking, the term alpha-fat specifies the shape of the region in comparison to a disk. We give the first approximation algorithm for this problem and achieve an approximation ratio of (1+epsilon)(9.093alpha +1). Last, we consider Manhattan networks. They are allowed to contain edges only in horizontal and vertical direction. In contrast to Steiner trees they contain a shortest path between each pair of points. We introduce insights into the structure of Manhattan networks, particularly in the context of so-called staircases. We give three new approximation algorithms for the Manhattan network problem, the first with approximation ratio 3 and two algorithms with ratio 2. To this end we introduce two algorithms for the Manhattan network problem of staircases. The first algorithm solves the problem to optimality the second yields a 2-approximation. Variants of both algorithms are already known in the literature. Since we use a slightly different definition of staircases and we need special properties of them, we adopt the algorithms to our situation. The 2-approximation algorithms achieve the best known approximation ratio of an algorithm for the Manhattan network problem known so far. Last we give an idea how we could possibly find an algorithm with better approximation ratio

05361 Abstracts Collection -- Algorithmic Aspects of Large and Complex Networks

From 04.09.05 to 09.09.05, the Dagstuhl Seminar 05361 ``Algorithmic Aspects of Large and Complex Networks\u27\u27 was held in the International Conference and Research Center (IBFI), Schloss Dagstuhl. During the seminar, several participants presented their current research, and ongoing work and open problems were discussed. Abstracts of the presentations given during the seminar as well as abstracts of seminar results and ideas are put together in this paper. The first section describes the seminar topics and goals in general. Links to extended abstracts or full papers are provided, if available

Shortest Paths and Steiner Trees in VLSI Routing

Routing is one of the major steps in very-large-scale integration (VLSI) design. Its task is to find disjoint wire connections between sets of points on a chip, subject to numerous constraints. This problem is solved in a two-stage approach, which consists of so-called global and detailed routing steps. For each set of metal components to be connected, global routing reduces the search space by computing corridors in which detailed routing sequentially determines the desired connections as shortest paths. In this thesis, we present new theoretical results on Steiner trees and shortest paths, the two main mathematical concepts in routing. In the practical part, we give computational results of BonnRoute, a VLSI routing tool developed at the Research Institute for Discrete Mathematics at the University of Bonn. Interconnect signal delays are becoming increasingly important in modern chip designs. Therefore, the length of paths or direct delay measures should be taken into account when constructing rectilinear Steiner trees. We consider the problem of finding a rectilinear Steiner minimum tree (RSMT) that --- as a secondary objective --- minimizes a signal delay related objective. Given a source we derive some structural properties of RSMTs for which the weighted sum of path lengths from the source to the other terminals is minimized. Also, we present an exact algorithm for constructing RSMTs with weighted sum of path lengths as secondary objective, and a heuristic for various secondary objectives. Computational results for industrial designs are presented. We further consider the problem of finding a shortest rectilinear Steiner tree in the plane in the presence of rectilinear obstacles. The Steiner tree is allowed to run over obstacles; however, if it intersects an obstacle, then no connected component of the induced subtree must be longer than a given fixed length. This kind of length restriction is motivated by its application in VLSI routing where a large Steiner tree requires the insertion of repeaters which must not be placed on top of obstacles. We show that there are optimal length-restricted Steiner trees with a special structure. In particular, we prove that a certain graph (called augmented Hanan grid) always contains an optimal solution. Based on this structural result, we give an approximation scheme for the special case that all obstacles are of rectangular shape or are represented by at most a constant number of edges. Turning to the shortest paths problem, we present a new generic framework for Dijkstra's algorithm for finding shortest paths in digraphs with non-negative integral edge lengths. Instead of labeling individual vertices, we label subgraphs which partition the given graph. Much better running times can be achieved if the number of involved subgraphs is small compared to the order of the original graph and the shortest path problems restricted to these subgraphs is computationally easy. As an application we consider the VLSI routing problem, where we need to find millions of shortest paths in partial grid graphs with billions of vertices. Here, the algorithm can be applied twice, once in a coarse abstraction (where the labeled subgraphs are rectangles), and once in a detailed model (where the labeled subgraphs are intervals). Using the result of the first algorithm to speed up the second one via goal-oriented techniques leads to considerably reduced running time. We illustrate this with the routing program BonnRoute on leading-edge industrial chips. Finally, we present computational results of BonnRoute obtained on real-world VLSI chips. BonnRoute fulfills all requirements of modern VLSI routing and has been used by IBM and its customers over many years to produce more than one thousand different chips. To demonstrate the strength of BonnRoute as a state-of-the-art industrial routing tool, we show that it performs excellently on all traditional quality measures such as wire length and number of vias, but also on further criteria of equal importance in the every-day work of the designer

New Approaches on Octilinear Graph Drawing

Graphenzeichnen ist ein Bereich der Informatik mit langer Tradition. Insbesondere im Bereich des orthogonalen Graphenzeichnens wird seit den 1980er Jahren motiviert durch VLSI-Design (Chip-Design) und Grundrissplanung intensiv geforscht. In dieser Arbeit wird das klassische orthogonale Modell durch neue Elemente, unter anderem aus dem oktilinearen Graphenzeichnen, erweitert. Die ersten Ergebnisse, die wir in dieser Arbeit vorstellen, befassen sich mit oktilinearem Graphenzeichnen. Dieses Modell ist altbekannt und viele Aspekte wurden schon untersucht. Wir entwickeln eine Methode mit der für planare Graphen mit einem beschränkten maximalen Knotengrad (4 und 5) Zeichnungen mit maximal einem Knick pro Kante erstellt werden können. Außerdem zeigen wir, dass Graphen mit maximalem Knotengrad 6 nicht immer mit einem Knick pro Kante gezeichnet werden können. Damit schließen wir die Lücke zwischen bekannten Ergebnissen, die besagen dass Graphen mit maximalem Knotengrad 3 immer ohne Knicke und alle Graphen bis zu einem maximalen Knotengrad von 8 mit höchstens zwei Knicken pro Kante oktilinear gezeichnet werden können. Durch Nutzerstudien konnte gezeigt werden, dass die Lesbarkeit von (Graphen) Zeichnungen durch Knicke auf den Kanten und schlecht identifizierbare Kreuzungen besonders beeinträchtigt wird. An diesem Punkt setzt unser neues Modell, das abgeschrägt orthogonale (engl. slanted orthogonal, oder kurz: slog) Graphenzeichnen an. Im slog Modell ist der kleinste erlaubte Winkel zwischen zwei aufeinander folgenden Kantensegmenten 135°. Das hat zur Folge, dass slog Zeichnungen keine normalen Knicke mehr haben, sondern sogenannte Halb-Knicke. Um Kreuzungen besser erkennbar zu machen sind im slog Modell Kreuzungen ausschließlich zwischen diagonalen Segmenten erlaubt. Wir zeigen, dass eine knick-minimale slog Zeichnung mindestens doppelt so viele Halb-Knicke benötigt, wie eine knick-minimale orthogonale Zeichnung Knicke hat. Für das slog Modell werden in dieser Arbeit Methoden zur Berechnung von knick-minimalen Zeichnungen vorgestellt. Da diese exponentielle Fläche benötigen können, wird außerdem eine Heuristik entwickelt, die nur quadratische Fl ̈ache benötigt, dafür aber mehr Knicke zulässt. Die Ergebnisse einer experimentellen Evaluation des slog Modells werden ebenfalls präsentiert. Im Anschluss erweitern wir das slog Modell zu einer flexibleren Variante die wir sloggy nennen. Das sloggy Modell hat alle Eigenschaften des slog Modells, aber Kreuzungen werden jetzt auch zwischen orthogonalen Segmenten erlaubt. Dafür wird die Anzahl Halb-Knicke beschränkt auf genau zwei Mal die Anzahl Knicke der entsprechenden knick-minimalen orthogonalen Zeichnung. Außerdem wird die Anzahl an Kreuzungen zwischen diagonalen Segmenten maximiert. Wir entwickeln eine Methode zur Berechnung solcher Zeichnungen und zeigen, dass auch hier exponentielle Fläche benötigt werden kann. Das slog und das sloggy Modell sind auf Graphen mit einem maximalen Knotengrad von 4 beschränkt. Deswegen wenden wir uns als nächstes dem Kandinsky Modell zu, einem bekannten Modell mit dem Graphen mit beliebigem Knotengrad gezeichnet werden können. Wir erweitern das bekannte Modell mit Elementen aus dem slog Modell, den Halb-Knicken, um so zuvor verbotene Konfigurationen zeichnen zu können. Mit unserer Erweiterung wollen wir die Gesamtzahl an Knicken und die Größe der Zeichnungen verkleinern. Wir entwickeln eine LP Formulierung, mit der die optimale Zeichnung berechnet werden kann. Da diese sehr lange Zeit zur Berechnung beanspruchen kann, haben wir zusätzliche eine effiziente Heuristik entwickelt. In einer experimentellen Untersuchung vergleichen wir außerdem das neue Modell mit dem klassischen Kandinsky Modell. Im letzten Kapitel vereinen wir dann unsere Modifikation des Kandinsky Modells mit dem slog Modell im sogenannten sloginsky Modell, um Graphen mit beliebigem Knotengrad mit den Vorteilen des slog Modells zeichnen zu können. Wir entwickeln eine Methode zur Berechnung knick-optimaler sloginsky Zeichnungen, aber wir zeigen auch, dass eine solche Zeichnung nicht für jede Eingabe möglich ist. Auch im sloginsky Modell kann eine Zeichnung exponentielle Fläche beanspruchen, was in der experimentellen Evaluation ebenfalls sichtbar wird

High-Performance Placement and Routing for the Nanometer Scale.

Modern semiconductor manufacturing facilitates single-chip electronic systems that only five years ago required ten to twenty chips. Naturally, design complexity has grown within this period. In contrast to this growth, it is becoming common in the industry to limit design team size which places a heavier burden on design automation tools. Our work identifies new objectives, constraints and concerns in the physical design of systems-on-chip, and develops new computational techniques to address them. In addition to faster and more relevant design optimizations, we demonstrate that traditional design flows based on ``separation of concerns'' produce unnecessarily suboptimal layouts. We develop new integrated optimizations that streamline traditional chains of loosely-linked design tools. In particular, we bridge the gap between mixed-size placement and routing by updating the objective of global and detail placement to a more accurate estimate of routed wirelength. To this we add sophisticated whitespace allocation, and the combination provides increased routability, faster routing, shorter routed wirelength, and the best via counts of published techniques. To further improve post-routing design metrics, we present new global routing techniques based on Discrete Lagrange Multipliers (DLM) which produce the best routed wirelength results on recent benchmarks. Our work culminates in the integration of our routing techniques within an incremental placement flow to improve detailed routing solutions, shrink die sizes and reduce total chip cost. Not only do our techniques improve the quality and cost of designs, but also simplify design automation software implementation in many cases. Ultimately, we reduce the time needed for design closure through improved tool fidelity and the use of our incremental techniques for placement and routing.Ph.D.Computer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/64639/1/royj_1.pd

Approximation of Octilinear Steiner Trees Constrained by Hard and Soft Obstacles

The novel octilinear routing paradigm (X-architecture) in VLSI design requires new approaches for the construction of Steiner trees. In this paper, we consider two versions of the shortest octilinear Steiner tree problem for a given point set K of terminals in the plane: (1) a version in the presence of hard octilinear obstacles, and (2) a version with rectangular soft obstacles. The interior of hard obstacles has to be avoided completely by the Steiner tree. In contrast, the Steiner tree is allowed to run over soft obstacles. But if the Steiner tree intersects some soft obstacle, then no connected component of the induced subtree may be longer than a given fixed length L. This kind of length restriction is motivated by its application in VLSI design where a large Steiner tree requires the insertion of buffers (or inverters) which must not be placed on top of obstacles. For both problem types, we provide reductions to the Steiner tree problem in graphs of polynomial size with the following approximation guarantees. Our main results are (1) a 2–approximation of the octilinear Steiner tree problem in the presence of hard rectilinear or octilinear obstacles which can be computed in O(n log 2 n) time, where n denotes the number of obstacle vertices plus the number of terminals, (2) a (2 + ε)–approximation of the octilinear Steiner tree problem in the presence of soft rectangular obstacles which runs in O(n 3) time, and (3) a polynomial time (1.55 + ε)– approximation of the octilinear Steiner tree problem in the presence of soft rectangular obstacles