Size, Speed, and Power Analysis for Application-Specific Integrated Circuits Using Synthesis

An application-specific integrated circuit (ASIC) must not only provide the required functionality at the desired speed but it must also be economical. In the past, minimizing the size of the ASIC was sufficient to accomplish this goal. Today it is increasingly necessary that the ASIC also achieve minimum power dissipation or an optimal combination of speed, size and power, especially in communication and portable electronic devices. The research reported in this thesis describes the implementation of a Huffman encoder and a finite impulse response (FIR) filter using a hardware description language (HDL) and the testing of the corresponding register transfer level (RTL) for functionality. The RTL was targeted for two different libraries, TSMC-0.18 CMOS and the Xilinx Virtex V1000EHQ240-6. The RTL was synthesized and optimized for different sizes, speeds, and power by using the Synopsys Design Compiler, FPGA Compiler II, and Mentor Graphics Spectrum. Cadence place and route tools optimized area, delay, and power of post-layout stages for TSMC-0.18. Xilinx place and route tools were used for the Virtex V1000EHQ240-6. The various ASICs were produced and compared over a range of speed, area, and power. i

End-of-fabrication CMOS process monitor

A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's)

A reconfigurable multicarrier demodulator architecture

An architecture based on parallel and pipline design approaches has been developed for the Frequency Division Multiple Access/Time Domain Multiplexed (FDMA/TDM) conversion system. The architecture has two main modules namely the transmultiplexer and the demodulator. The transmultiplexer has two pipelined modules. These are the shared multiplexed polyphase filter and the Fast Fourier Transform (FFT). The demodulator consists of carrier, clock, and data recovery modules which are interactive. Progress on the design of the MultiCarrier Demodulator (MCD) using commercially available chips and Application Specific Integrated Circuits (ASIC) and simulation studies using Viewlogic software will be presented at the conference

The Advent of Application Specific Integrated Circuits (ASIC)-MEMS within the Medical System

Medical healthcare has become one of the fastest growing and largest industries in the world. More and more people are aware of the precious and important life. At the same time, personal disposable income increases and awareness of disease prevention increases. It allows the healthcare industry to maintain high growth rates. Micro-electro- mechanical systems (MEMS) is one of the most revolutionary semiconductor components. The advent of Application Specific Integrated Circuits (ASIC)-MEMS has created a new era for the healthcare industry. The medical Micro LED detects the blood vessel position with the emission light source and repositions the blood flow state of the blood vessel. Micro LED mainly uses the MEMS micro-fabrication technology to micronize, array, and thin film the traditional LED crystal film. This article will explore how to use MEMS wafers to redefine the needs of the healthcare market and open up new growth opportunities for healthcare applications. With the shift from first-hand medical devices from the hospital business to personal use, miniaturization, economics, reliability and battery life have become new demands in the healthcare market

Tomographic Application-Specific Integrated Circuits for Fast Radon Transformation

The application-specific integrated circuit (ASIC) for tomographic processing of point objects is developed. The processing method is based on discrete Radon transform. We constructed modified method of replacing Radon transform with Fourier transform using interpolation on quasi-regular coordinate grids – regular with constant step on lengthwise coordinate and linearly growing step with constant difference on transverse coordinate. The resulting grid is quasi-regular and calculating complexity become significantly smaller. Grounding on concept of separate differences of arbitrary order we overcome the problem of irregularity of coordinate grids. The applied-specific tomographic circuit for processing 2D signals is constructed and three-level automated control technological processes system is developed