Stress-Induced Delamination Of Through Silicon Via Structures

Continuous scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32 nm technology node in microelectronics. Recently three-dimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effect of thermal stresses on interfacial reliability of TSV structures. First, the three-dimensional distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semi-analytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results obtained by finite element analysis (FEA). Results from the stress analysis suggest interfacial delamination as a potential failure mechanism for the TSV structure. Analytical solutions for various TSV designs are then obtained for the steady-state energy release rate as an upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. Based on these results, the effects of TSV designs and via material properties on the interfacial reliability are elucidated. Finally, potential failure mechanisms for TSV pop-up due to interfacial fracture are discussed.Aerospace Engineerin

Thermomechanical Reliability Challenges For 3D Interconnects With Through-Silicon Vias

Continual scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32 nm technology node in microelectronics. Recently threedimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Among others, thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effects of thermally induced stresses on interfacial reliability of TSV structures. First, three-dimensional distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semi-analytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results From finite element analysis (FEA). The stress analysis suggests interfacial delamination as a potential failure mechanism for the TSV structure. An analytical solution is then obtained for the steady-state energy release rate as the upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. With these results, the effects of the TSV dimensions (e.g., via diameter and wafer thickness) on the interfacial reliability are elucidated. Furthermore, the effects of via material properties are discussed.Aerospace Engineerin

Using far-field measurements for determining mixed-mode interactions at interfaces

Traction–separation relations (TSR) can be used to represent the interactions at a bimaterial interface during fracture and adhesion. The goal of this work is to develop a direct method to extract mixed-mode TSRs using only the far-field measurements. The first topic of the dissertation deals with extracting mixed-mode TSRs based on a combination of global and local measurements including load-displacement, crack extension, crack tip opening displacement, and fracture resistance curves. Mixed-mode interfacial fracture experiments were conducted using the end loaded split (ELS) configuration for a silicon-epoxy interface, where the epoxy thickness was used to control the phase angle of the fracture mode-mix. Infra-red crack opening interferometry (IR-COI) was used to measure the normal crack opening displacements. For the resistance curves, an approximate value of the J-integral was calculated based on a beam-on-elastic-foundation model that referenced the measured load-displacement data. A damage-based cohesive zone model with mixed-mode TSRs was then adopted in finite element analyses, with the interfacial properties determined directly from the experiments. With the mode-I fracture toughness from a previous study, the model was used to predict mixed-mode fracture of a silicon/epoxy interface for phase angles ranging from -42˚ to 0˚. Additional measurements would be necessary to further extend the reach of the model to mode-II dominant conditions. The second topic of the dissertation addresses characterization of interfacial interactions between copper through-silicon vias (TSV) and silicon substrates. A suitable choice of via length allowed a direct method to be implemented for determining the mode-II traction-separation relation between silicon and copper TSVs. This interface was loaded in a nano-indentation experiment on specimens with pre cracks that were fabricated using focused-ion-beam (FIB) milling. The elastic and plastic properties of the copper vias were characterized from micro-pillar compression experiments and associated finite element analyses. Analytical and numerical models were developed for extracting the parameters of traction-separation relation. The third topic of the dissertation explores a more general approach to directly extract the mixed-mode traction-separation relations using only far-field measurements from laminated beam specimens. Balanced laminated beam configurations were used to conduct the mixed-mode fracture experiment on a silicon-epoxy interface. The far-field measurements included the displacement at the middle of the bottom adherend at a point behind of the crack front, the force-displacement response, and the angle of rotation at the end of the top adherend. With these far-field measurements, the J integrals in mode-I and mode-II could be calculated separately when the ratio between the thickness and the bending stiffness is the same for both the top and bottom adherends. The local separations at the crack tip are also calculated using these far-field measurements. The traction-separation relations are then obtained directly through numerical differentiation of the obtained J integral with respect to the local separations. This method was validated by comparing to the local measurements of normal separation using IR-COI technique. The extracted normal and shear TSR showed decoupled behavior in damage initiation and evolution which indicate that it is impossible to model using potential-based TSRs. A promising attempt was made to subtract out the elastic deformations of the epoxy that was used in this work. This was achieved by conducting a cohesive zone analysis using an extracted pair of normal and shear traction-separation relations for a particular mode-mix without the epoxy between the adherends.Engineering Mechanic

Study of through-silicon-vias (TSVs) induced transistor variation

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 83-85).As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidth and power efficiency. Through-siliconvias (TSVs), which directly connect stacked structures die-to-die, is one of the key techniques enabling 3D integration. The process steps and physical presence of TSVs, however, may generate a stress-induced thermal mismatch between TSVs and the silicon bulk. These effects could further perturb the performance of nearby electronic structures, particularly transistors, diodes, and associated circuits. This thesis presents a comprehensive study to characterize, analyze and model the impact of TSV-induced stress impact on device and circuit performance and its interaction with polysilicon and shallow-trench-isolation (STI) layout pattern density. A test chip is designed with multiplexing test circuits providing measurements of key parameters of a large number of devices. These devices under test (DUTs) have layouts that explore a range of TSV and device layout choices in the design of experiments (DOEs). The test chip uses a scan chain approach combined with low-leakage and low-variation switches and Kelvin sensing connections, which provide access to detailed analog device characteristics in large arrays of test devices. A test circuit and an Ioff measurement method is designed to perform off-chip wafer probe testing measurement. In addition, a finite element analysis model is constructed to mimic realistic TSV structures and processes. A complete flow and methodology to analyze transistor characteristics and circuit performance under the influence of TSV stress is proposed. An efficient algorithm is also proposed to simulate full-chip circuit variation under the impact of TSV stress based on a grid partition approach. Test cases corresponding to the aforementioned test chip are simulated for comparison with measurement data.by Li Yu.S.M

Laser-driven micro-transfer printing for MEMS/NEMS integration

Heterogeneous materials integration, motivated by material transfer processes, has evolved to address the technology gap between the conventional micro-fabrication processes and multi-layer functional device integration. In its basic embodiment, micro-transfer printing is used to deterministically transfer and micro-assemble prefabricated microstructures/devices, referred to as “ink,” from donor substrates to receiving substrates using a viscoelastic elastomer stamp, usually made out of polydimethylsiloxane (PDMS). Thin-film release is, in general, difficult to achieve at the micro-scale (surface effects dominate). However, it becomes dependent on the receiving substrate’s properties and preparation. Laser Micro-Transfer Printing (LMTP) is a laser-driven version of the micro-transfer printing process that enables non-contact release of the microstructure by inducing a mismatch thermal strain at the ink-stamp interface; making the transfer printing process independent from the properties or preparation of the receiving substrate. In this work, extensive studies are conducted to characterize, model, predict, and improve the capabilities of the LMTP process in developing a robust non-contact pattern transfer process. Using micro-fabricated square silicon inks and varying the lateral dimensions and thickness of the ink, the laser pulse duration required to drive the delamination, referred to as “delamination time,” is experimentally observed using high-speed camera recordings of the delamination process for different laser beam powers. The power absorbed by the ink is measured to estimate the total energy stored in the ink-stamp system and available to initiate and propagate the delamination crack at the interface. These experiments are used as inputs for an opto-thermo-mechanical model to understand how the laser energy is converted to thermally-induced stresses at the ink-stamp interface to release the inks. The modeling approach is based on first developing an analytical optical absorption model, based on Beer-Lambert law, under the assumption that optical absorption during the LMTP process is decoupled from thermo-mechanical physics. The optical absorption model is used to estimate the heating rate of the ink-stamp system during the LMTP process that, in turn, is used as an input to the coupled thermo-mechanical Finite Element Analysis (FEA) model. Fracture mechanics quantities such as the Energy Release Rate (ERR) and the Stress Intensity Factors (SIFs) are estimated using the model. Then, the thermal stresses at the crack tip, evaluated by the SIFs, are decomposed into two components based on originating causes: CTE mismatch between the ink and the stamp, and thermal gradient within the PDMS stamp. Both the delamination time from the high-speed camera experiments and thermo-mechanical FEA model predictions are used to understand and improve the process’s performance under different printing conditions. Several studies are conducted to understand the effect of other process parameters such as the dimensions and materials of the stamp, the ink-stamp alignment, and the transferred silicon ink shape on the process performance and mechanism. With an objective of reducing the delamination time, the delamination energy, and the temperature of the ink-stamp interface during printing, different patterned stamp designs (cavity, preloading, and thin-walls) have been proposed. Cavity, preloading, and thin-wall stamps are designed to generate thermally-induced air pressure at the ink-stamp interface, to store strain energy at the interface, and to generate thermally-induced air pressure at the preloaded interface, respectively. Cohesive Zone Modeling (CZM) based models are developed to estimate the equilibrium solution of the collapsed patterned stamp after the ink pick-up process, and to evaluate the patterned stamps’ performance during the LMTP process. The patterned stamps show significant improvements in delamination times and delamination energies (up to 35%) and acceptable improvement of the interface temperature at the delamination point (up to 16%) for given printing conditions

Design, fabrication, and reliability study of second-level compliant microelectronic interconnects

Free-standing off-chip interconnects have high in-plane and out-of-plane compliance and are being pursued in academia and industry to reduce die stresses and to enhance interconnect reliability. The geometry of the compliant interconnect, its dimensions, and the material and processes used for fabricating the interconnect influence its mechanical and electrical characteristics, fabrication and assembly yield, thermo-mechanical and drop-impact reliability, and cost of fabrication. Although studies have examined various compliant interconnect designs, a multi-objective and multi-physics design optimization of the compliant interconnect has not been adequately pursued and implemented in prototypes. The first objective of this thesis is to develop a second-level multi-path compliant interconnect for microelectronic systems by performing compliance analysis and multi-physics design optimization using analytical and numerical models; The second objective of this thesis is to develop dry-film based sequential processes to fabricate such compliant interconnects on a silicon wafer, and to assemble singulated silicon substrates on organic printed circuit boards. In particular, in this work, the fabricated interconnects form a 45 × 45 array on the 18 mm × 18 mm silicon substrate. Several variations of the interconnects have been fabricated with the arcuate beam having a width of 10, 15, and 20µm on a footprint of 280µm, and with a pitch of 400µm. The third objective of this work is to experimentally demonstrate the thermal cycling reliability of the assemblies, and to validate the results from numerical models. The fourth objective is to experimentally demonstrate that compliant interconnects can effectively isolate the silicon substrate from the board under drop impact conditions, and to determine the reliability of the interconnects under drop impact conditions. It is seen that the compliant interconnects are able to isolate the silicon substrate from the board, and the board-to-substrate strain ratios are 21.55, 9.53 and 7.01 for compliant interconnects with arcuate beam width equal to 10μm, 15μm and 20μm, respectively, compared to 2.46 for solder ball interconnects. The experimental drop impact results are used for validating the drop-impact simulation predictions. Overall, by combining cleanroom fabrication, assembly, thermal cycling and drop-impact testing with analytical and numerical models as well as design optimization, this work provides a comprehensive insight into the development of multi-path copper structures as second-level microsystem interconnects.Ph.D

Micro/Nano Structures and Systems

Micro/Nano Structures and Systems: Analysis, Design, Manufacturing, and Reliability is a comprehensive guide that explores the various aspects of micro- and nanostructures and systems. From analysis and design to manufacturing and reliability, this reprint provides a thorough understanding of the latest methods and techniques used in the field. With an emphasis on modern computational and analytical methods and their integration with experimental techniques, this reprint is an invaluable resource for researchers and engineers working in the field of micro- and nanosystems, including micromachines, additive manufacturing at the microscale, micro/nano-electromechanical systems, and more. Written by leading experts in the field, this reprint offers a complete understanding of the physical and mechanical behavior of micro- and nanostructures, making it an essential reference for professionals in this field

Thermal Isolation of High Power Devices in Heterogeneous Integration

Heterogeneous integration (HI) technologies present an important development in the pursuit of higher performance and reduced size, weight, power and cost of electronic systems (SWAP-C). HI systems, however, pose additional challenges for thermal management due to the disparate operating conditions of the devices. If the thermal coupling between devices can be reduced through a strategy of thermal isolation, then the SWAP-C of the accompanying thermal solution can also be reduced. This is in contrast to the alternative scenario of cooling the entire package to the maximum reliable temperature of the most sensitive devices. This isolation strategy must be implemented without a significant increase in device interconnect distances. A counter-intuitive approach is to seek packaging materials of low thermal conductivity – e.g. glass – and enhance them with arrays of metallic through-layer vias. This dissertation describes the first ever demonstration of integrating such via-enhanced interposers with microfluidic cooling, a thermal solution key to the high power applications for which HI was developed. Among the interposers tested, the best performing were shown to exhibit lower thermal coupling than bulk silicon in selective regions, validating their ability to provide thermal isolation. In the course of the study, the via-enhanced interposer is modeled as a thermal metamaterial with desirable, highly-anisotropic properties. Missing from the supporting literature is an accurate treatment of these interposers under such novel environments as microfluidic cooling. This dissertation identifies a new phenomenon, thermal microspreading, which governs how heat couples into a conductive via array from its surroundings. Both finite element analysis (FEA) and a new analytic solution of the associated boundary value problem (BVP) are used to develop a model for describing microspreading. This improves the ability to correctly predict the thermal behavior of via-enhanced interposers under diverse conditions