Compact DC Modeling of Tunnel-FETs

En l'última dècada, el transistor d'efecte de camp amb efecte túnel (TFET) ha guanyat molt interès i es maneja com un possible successor de la tecnologia MOSFET convencional. El transport de càrrega en un TFET es basa en el mecanisme de túnel de banda a banda (B2B) i, per tant, el pendent sub-llindar a temperatura ambient pot superar el límit de 60 mV / dec. Per descriure i analitzar el comportament del TFET en les simulacions de circuits, aquesta dissertació introdueix un model compacte de CC per TFET de doble comporta. L'enfocament de modelatge considera l'efecte túnel B2B amb l'efecte parasitari del corrent túnel assistida per trampes (TAT) en l'estat ON i ambipolar del TFET. Inclou un paquet d'equacions compactes per al potencial 2D per descriure el diagrama de banda del TFET. Basat en el diagrama de banda, el B2B i el corrent TAT es deriven per separat. Per fer-ho, primer es troba una expressió compacta per la llargada túnel, que després s'utilitza juntament amb un enfocament numèric robust de tipus Wentzel-Kramers-Brillouin (WKB) per calcular la probabilitat túnel. Després, usant l'equació de túnel de Landauer, la taxa de generació túnel es calcula i s'aproxima per arribar a una expressió de forma tancada per a la densitat de corrent. Amb una aproximació addicional de la densitat de corrent utilitzant una funció matemàtica, s'aconsegueixen expressions compactes per al túnel B2B resultant i el corrent TAT. La verificació del model es realitza amb l'ajuda de les dades de simulació TCAD Sentaurus per diverses configuracions de simulació. A més, la validesa del model es demostra mitjançant mesuraments de TFET complementaris fabricats. Per demostrar l'estabilitat numèrica i la continuïtat, així com la flexibilitat, es realitzen i analitzen simulacions de circuits lògics basats en TFET com un inversor d'una sola etapa o una cel·la SRAM. La combinació del model CC amb un model TFET AC permet una simulació transitòria d'un oscil·lador en anell de 11 etapes.En la última década, el transistor de efecto de campo con efecto túnel (TFET) ha ganado mucho interés y se maneja como un posible sucesor de la tecnología MOSFET convencional. El transporte de carga en un TFET se basa en el mecanismo de túnel de banda a banda (B2B) y, por lo tanto, la pendiente sub-umbral a temperatura ambiente puede superar el límite de 60 mV / dec. Para describir y analizar el comportamiento del TFET en las simulaciones de circuitos, esta disertación introduce un modelo compacto de CC para TFET de doble compuerta. El enfoque de modelado considera el efecto túnel B2B con el efecto parasitario de la corriente túnel asistida por trampas (TAT) en el estado ON y AMBIPOLAR del TFET. Incluye un paquete de ecuaciones compactas del potencial 2D para describir el diagrama de banda del TFET. Basado en el diagrama de banda, el B2B y la corriente TAT se derivan por separado. Para hacerlo, primero se encuentra una expresión compacta para la longitud túnel, que luego se utiliza junto con un enfoque numérico robusto de tipo Wentzel-Kramers-Brillouin (WKB) para calcular la probabilidad túnel. Luego, usando la ecuación de túnel de Landauer, la tasa de generación túnel se calcula y aproxima para llegar a una expresión de forma cerrada para la densidad de corriente. Con una aproximación adicional de la densidad de corriente por una función matemática, se logran expresiones compactas para el túnel B2B resultante y la corriente TAT. La verificación del modelo se realiza con la ayuda de los datos de simulación TCAD Sentaurus para varias configuraciones de simulación. Además, la validez del modelo se demuestra mediante mediciones de TFET complementarios fabricados. Para demostrar la estabilidad numérica y la continuidad, así como la flexibilidad, se realizan y analizan simulaciones de circuitos lógicos basados en TFET como un inversor de una sola etapa o una celda SRAM. La combinación del modelo CC con un modelo TFET AC permite una simulación transitoria de un oscilador en anillo de 11 etapas.In the last decade, the tunnel field-effect transistor (TFET) has gained a lot of interest and is handled as a possible successor of the conventional MOSFET technology. The current transport of a TFET is based on the band-to-band (B2B) tunneling mechanism and therefore, the subthreshold slope at room temperature can overcome the limit of 60 mV/dec. In order to describe and analyze the TFET behavior in circuit simulations, this dissertation introduces a compact DC model for double-gate TFETs. The modeling approach considers the B2B tunneling and the parasitic effect of trap-assisted tunneling (TAT) in the ON- and AMBIPOLAR-state of the TFET. It includes a 2D compact potential equation package to de-scribe the band diagram of the TFET. Based on the band diagram, the B2B tunneling and TAT current part are derived separately. In order to do so, firstly a compact expression for the tunneling length is found, which is then used together with a numerical robust Wentzel-Kramers-Brillouin (WKB) approach to calculate the tunneling probability. Afterwards, using Landauer’s tunneling equation, the tunneling generation rate is calculated and approximated to come to a closed-form expression for the current density. Further approximation of the current density by a mathematical function, compact expressions for the resulting B2B tun-neling and TAT current are achieved. The verification of the model is done with the help of TCAD Sentaurus simulation data for various simulation setups. Furthermore, the validity of the model is proven by measurements of fabricated complementary TFETs. In order to demonstrate the numerical stability and continuity as well as the flexibility, simulations of TFET-based logic circuits like a single-stage inverter or an SRAM cell are performed and analyzed. The combination of the DC model with an TFET AC model allows for a transient simulation of an 11-stage ring oscillator

Compact DC Modeling of Tunnel-FETs

En l'última dècada, el transistor d'efecte de camp amb efecte túnel (TFET) ha guanyat molt interès i es maneja com un possible successor de la tecnologia MOSFET convencional. El transport de càrrega en un TFET es basa en el mecanisme de túnel de banda a banda (B2B) i, per tant, el pendent sub-llindar a temperatura ambient pot superar el límit de 60 mV / dec. Per descriure i analitzar el comportament del TFET en les simulacions de circuits, aquesta dissertació introdueix un model compacte de CC per TFET de doble comporta. L'enfocament de modelatge considera l'efecte túnel B2B amb l'efecte parasitari del corrent túnel assistida per trampes (TAT) en l'estat ON i ambipolar del TFET. Inclou un paquet d'equacions compactes per al potencial 2D per descriure el diagrama de banda del TFET. Basat en el diagrama de banda, el B2B i el corrent TAT es deriven per separat. Per fer-ho, primer es troba una expressió compacta per la llargada túnel, que després s'utilitza juntament amb un enfocament numèric robust de tipus Wentzel-Kramers-Brillouin (WKB) per calcular la probabilitat túnel. Després, usant l'equació de túnel de Landauer, la taxa de generació túnel es calcula i s'aproxima per arribar a una expressió de forma tancada per a la densitat de corrent. Amb una aproximació addicional de la densitat de corrent utilitzant una funció matemàtica, s'aconsegueixen expressions compactes per al túnel B2B resultant i el corrent TAT. La verificació del model es realitza amb l'ajuda de les dades de simulació TCAD Sentaurus per diverses configuracions de simulació. A més, la validesa del model es demostra mitjançant mesuraments de TFET complementaris fabricats. Per demostrar l'estabilitat numèrica i la continuïtat, així com la flexibilitat, es realitzen i analitzen simulacions de circuits lògics basats en TFET com un inversor d'una sola etapa o una cel·la SRAM. La combinació del model CC amb un model TFET AC permet una simulació transitòria d'un oscil·lador en anell de 11 etapes.En la última década, el transistor de efecto de campo con efecto túnel (TFET) ha ganado mucho interés y se maneja como un posible sucesor de la tecnología MOSFET convencional. El transporte de carga en un TFET se basa en el mecanismo de túnel de banda a banda (B2B) y, por lo tanto, la pendiente sub-umbral a temperatura ambiente puede superar el límite de 60 mV / dec. Para describir y analizar el comportamiento del TFET en las simulaciones de circuitos, esta disertación introduce un modelo compacto de CC para TFET de doble compuerta. El enfoque de modelado considera el efecto túnel B2B con el efecto parasitario de la corriente túnel asistida por trampas (TAT) en el estado ON y AMBIPOLAR del TFET. Incluye un paquete de ecuaciones compactas del potencial 2D para describir el diagrama de banda del TFET. Basado en el diagrama de banda, el B2B y la corriente TAT se derivan por separado. Para hacerlo, primero se encuentra una expresión compacta para la longitud túnel, que luego se utiliza junto con un enfoque numérico robusto de tipo Wentzel-Kramers-Brillouin (WKB) para calcular la probabilidad túnel. Luego, usando la ecuación de túnel de Landauer, la tasa de generación túnel se calcula y aproxima para llegar a una expresión de forma cerrada para la densidad de corriente. Con una aproximación adicional de la densidad de corriente por una función matemática, se logran expresiones compactas para el túnel B2B resultante y la corriente TAT. La verificación del modelo se realiza con la ayuda de los datos de simulación TCAD Sentaurus para varias configuraciones de simulación. Además, la validez del modelo se demuestra mediante mediciones de TFET complementarios fabricados. Para demostrar la estabilidad numérica y la continuidad, así como la flexibilidad, se realizan y analizan simulaciones de circuitos lógicos basados en TFET como un inversor de una sola etapa o una celda SRAM. La combinación del modelo CC con un modelo TFET AC permite una simulación transitoria de un oscilador en anillo de 11 etapas.In the last decade, the tunnel field-effect transistor (TFET) has gained a lot of interest and is handled as a possible successor of the conventional MOSFET technology. The current transport of a TFET is based on the band-to-band (B2B) tunneling mechanism and therefore, the subthreshold slope at room temperature can overcome the limit of 60 mV/dec. In order to describe and analyze the TFET behavior in circuit simulations, this dissertation introduces a compact DC model for double-gate TFETs. The modeling approach considers the B2B tunneling and the parasitic effect of trap-assisted tunneling (TAT) in the ON- and AMBIPOLAR-state of the TFET. It includes a 2D compact potential equation package to de-scribe the band diagram of the TFET. Based on the band diagram, the B2B tunneling and TAT current part are derived separately. In order to do so, firstly a compact expression for the tunneling length is found, which is then used together with a numerical robust Wentzel-Kramers-Brillouin (WKB) approach to calculate the tunneling probability. Afterwards, using Landauer’s tunneling equation, the tunneling generation rate is calculated and approximated to come to a closed-form expression for the current density. Further approximation of the current density by a mathematical function, compact expressions for the resulting B2B tun-neling and TAT current are achieved. The verification of the model is done with the help of TCAD Sentaurus simulation data for various simulation setups. Furthermore, the validity of the model is proven by measurements of fabricated complementary TFETs. In order to demonstrate the numerical stability and continuity as well as the flexibility, simulations of TFET-based logic circuits like a single-stage inverter or an SRAM cell are performed and analyzed. The combination of the DC model with an TFET AC model allows for a transient simulation of an 11-stage ring oscillator

Silicon on ferroelectric insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

Title from PDF of title page, viewed on March 12, 2014Thesis advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 116-131)Thesis (M. S.)--School of Computer and Engineering. University of Missouri--Kansas City, 2013Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in subnanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor’s Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-lowpower applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.Abstract -- List of illustrations - List of tables -- Acknowledgements -- Dedication -- Introduction -- Carbon nanotube field effect transistor -- Multi-gate transistors -FinFET -- Subthreshold swing -- Tunneling field effect transistors -- I-mos and nanowire fets -- Ferroelectric based field effect transistors -- An analytical model to approximate the subthreshold swing for soi-finfet -- Silicon-on-ferroelectric insulator field effect transistor (SOF-FET) -- Current-voltage characteristics of sof-fet -- Advantages, manufacturing process and future work of the proposed device -- Appendix -- Reference

Sub-10nm Transistors for Low Power Computing: Tunnel FETs and Negative Capacitance FETs

One of the major roadblocks in the continued scaling of standard CMOS technology is its alarmingly high leakage power consumption. Although circuit and system level methods can be employed to reduce power, the fundamental limit in the overall energy efficiency of a system is still rooted in the MOSFET operating principle: an injection of thermally distributed carriers, which does not allow subthreshold swing (SS) lower than 60mV/dec at room temperature. Recently, a new class of steep-slope devices like Tunnel FETs (TFETs) and Negative-Capacitance FETs (NCFETs) have garnered intense interest due to their ability to surpass the 60mV/dec limit on SS at room temperature. The focus of this research is on the simulation and design of TFETs and NCFETs for ultra-low power logic and memory applications. Using full band quantum mechanical model within the Non-Equilibrium Greens Function (NEGF) formalism, source-underlapping has been proposed as an effective technique to lower the SS in GaSb-InAs TFETs. Band-tail states, associated with heavy source doping, are shown to significantly degrade the SS in TFETs from their ideal value. To solve this problem, undoped source GaSb-InAs TFET in an i-i-n configuration is proposed. A detailed circuit-to-system level evaluation is performed to investigate the circuit level metrics of the proposed devices. To demonstrate their potential in a memory application, a 4T gain cell (GC) is proposed, which utilizes the low-leakage and enhanced drain capacitance of TFETs to realize a robust and long retention time GC embedded-DRAMs. The device/circuit/system level evaluation of proposed TFETs demonstrates their potential for low power digital applications. The second part of the thesis focuses on the design space exploration of hysteresis-free Negative Capacitance FETs (NCFETs). A cross-architecture analysis using HfZrOx ferroelectric (FE-HZO) integrated on bulk MOSFET, fully-depleted SOI-FETs, and sub-10nm FinFETs shows that FDSOI and FinFET configurations greatly benefit the NCFET performance due to their undoped body and improved gate-control which enables better capacitance matching with the ferroelectric. A low voltage NC-FinFET operating down to 0.25V is predicted using ultra-thin 3nm FE-HZO. Next, we propose one-transistor ferroelectric NOR type (Fe-NOR) non-volatile memory based on HfZrOx ferroelectric FETs (FeFETs). The enhanced drain-channel coupling in ultrashort channel FeFETs is utilized to dynamically modulate memory window of storage cells thereby resulting in simple erase-, program-and read-operations. The simulation analysis predicts sub-1V program/erase voltages in the proposed Fe-NOR memory array and therefore presents a significantly lower power alternative to conventional FeRAM and NOR flash memories

Dielectric-Modulated TFETs as Label-Free Biosensors

This chapter presents tunnel field effect transistors (TFETs) as dielectric-modulated (DM) label-free biosensors, and discusses various aspects related to them. A brief survey of the dielectric-modulated TFET biosensors is presented. The concept of dielectric modulation in TFETs is discussed with focus on principle and design perspectives. A Technology Computer Aided Design (TCAD) based approach to incorporate embedded nanogaps in TFET geometries along with appropriate physics-based simulation models are mentioned. Non-ideal conditions in dielectric-modulated biosensors are brought to light, keeping in view the practical considerations of the devices. A gate engineered TFET is taken up for analysis of sensitivities under different conditions through TCAD simulations. Finally, a status map of the sensitivities of the most significant works in dielectric-modulated label-free biosensors is depicted, and the status of the proposed TFET is highlighted

Toward Nanowire Electronics

This paper discusses the electronic transport properties of nanowire field-effect transistors (NW-FETs). Four different device concepts are studied in detail: Schottky-barrier NW-FETs with metallic source and drain contacts, conventional-type NW-FETs with doped NW segments as source and drain electrodes, and, finally, two new concepts that enable steep turn-on characteristics, namely, NW impact ionization FETs and tunnel NW-FETs. As it turns out, NW-FETs are, to a large extent, determined by the device geometry, the dimensionality of the electronic transport, and the way of making contacts to the NW. Analytical as well as simulation results are compared with experimental data to explain the various factors impacting the electronic transport in NW-FETs

Modeling and Simulation of a TFET-Based Label-Free Biosensor with Enhanced Sensitivity

This study discusses the use of a triple material gate (TMG) junctionless tunnel field-effect transistor (JLTFET) as a biosensor to identify different protein molecules. Among the plethora of existing types of biosensors, FET/TFET-based devices are fully compatible with conventional integrated circuits. JLTFETs are preferred over TFETs and JLFETs because of their ease of fabrication and superior biosensing performance. Biomolecules are trapped by cavities etched across the gates. An analytical mathematical model of a TMG asymmetrical hetero-dielectric JLTFET biosensor is derived here for the first time. The TCAD simulator is used to examine the performance of a dielectrically modulated label-free biosensor. The voltage and current sensitivity of the device and the effects of the cavity size, bioanalyte electric charge, fill factor, and location on the performance of the biosensor are also investigated. The relative current sensitivity of the biosensor is found to be about 1013. Besides showing an enhanced sensitivity compared with other FET- and TFET-based biosensors, the device proves itself convenient for low-power applications, thus opening up numerous directions for future research and applications

Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems

In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the adaptive optimal reverse body-bias voltage. The adaptive optimal body-bias voltage is generated from the proposed leakage monitoring circuit, which compares the subthreshold current (ISUB) and the band-to-band tunneling (BTBT) current (IBTBT). The proposed circuit was simulated in HSPICE using 32-nm bulk CMOS technology and evaluated using ISCAS85 benchmark circuits at different operating temperatures (ranging from 25°C to 100°C). Analysis of the results shows a maximum of 551 and 1491 times leakage power reduction at 25°C and 100°C, respectively, on a circuit with 546 gates. The proposed approach demonstrates that the optimal body bias reduces a considerable amount of standby leakage power dissipation in nanoscale CMOS integrated circuits. In this approach, the temperature and supply voltage variations are compensated by the proposed feedback loop

Investigation of advanced GaN HEMTs for digital and high frequency applications

The physical features of Gallium nitride (GaN) and the related materials make them very suitable for the fabrication of power semiconductor devices. The large band gap and high electrical breakdown field strength of GaN in combination with high-density two-dimensional electron gases induced by polarization in AlGaN/GaN interface enables the development of transistors with high off-state voltages, low on-state resistances and low switching charges. However the transistors made of conventional GaN HEMTs have already approached their performance limit. In order to meet the future needs of power semiconductor devices, research efforts are being put on nonclassical HEMT concepts e.g. superjunction GaN HEMTs, PNT GaN HEMTs and GaN MIS FETs or on using a new barrier materials such AlScN and AlYN. This work aims to push GaN technology by new approaches in design and characterization of highly-efficient GaN transistors in order to release its full potential. The aim of the present work is the evaluation of different nonclassical GaN HEMT concepts regarding their performance and suitability for logic, power-switching and RF ampflication applications and to define their design space. The investigations are based on numerical device simulations supported by analytical calculations. It is shown that the simple and robust drift-diffusion model is well suited for the simulation of such nonclassical devices. The co-existence of two dimensional- electron and hole gases in GaN-based heterostructures is investigated by means of analytical models, developed in the frame of this work, and self-consistent numerical solutions of the Schrödinger and Poisson equations. It is shown that for certain combinations of bias conditions and layer design coexisting 2DEGs and 2DHGs can be formed in GaN/AlGaN/GaN structures, where the 2DHG is located at the cap/barrier interface and the 2DEG resides at the barrier/bulk interface. Once a 2DHG is created, the effect of the gate voltage on the 2DEG diminishes rapidly and a saturation of the 2DEG density is observed. Furthermore, in structures with thin barriers it is much more difficult to create a 2DHG even for large surface potentials. The formation of second channel in AlGaN/GaN/AlGaN/GaN heterostructures has been investigated. It has been shown that for certain combinations of bias conditions and layer design coexisting two channels can be formed in AlGaN2/GaN2/AlGaN1/GaN1 structures where both channels are located at the AlGaN1/GaN1 and AlGaN2/GaN2. Once a second channel is created, the effect of the gate voltage on the first 2DEG diminishes rapidly and a saturation of the drain current is observed. Special attention was paid to a novel vertical inverter design by employing these two channels. On the other hand, theoretical investigations of AlGaN/GaN HEMT structures for power switch applications focus on the estimation of oxide interface charges in MIS HEMT structures and on two simulation studies dealing with alternative normally-off HEMT concepts. The study on oxide interface charges is based on a comparison of measured and simulated threshold voltages of HEMTs with and without an oxide layer underneath the gate. Moreover, we developed a simple analytical threshold voltage model for the MIS HEMT structure which can be used to estimate the interface charge with a pocket calculator. We propose also a new approach to combine the effect of a p-type doped cap layer with that of a gate oxide for designing and achieving normally-off HEMT. We focus on the structures proposed by Ota et al. using 1D Schrödinger-Poisson simulations and analytical models. In particular, our analytical model shows that the threshold voltage is independent on the thicknesses of both the PNT layer and the strained GaN channel layer. Additionally, we discuss options to increase the electron sheet density in the ungated regions in order to reduce the source/drain resistances. Moreover, gated cubic InGaN/InN heterostructures for application in InN-based HEMTs are investigated theoretically. The formation of two-dimensional carrier gases in InGaN/InN structures is studied in detail and design issues for the InGaN barrier are investigated. It is shown that for certain surface potentials an undesirable saturation of the sheet density of the electron gas in the InN channel layer may occur. Options to enhance the electron sheet density in the channel and surface potential ranges for proper transistor operation are presented. Finally, the formation of two-dimensional electron gases in lattice-matched AlScN/GaN and AlYN/GaN heterostructures is investigated by numerical self-consistent solutions of the Schrödinger and Poisson equations. The electron concentration profiles and the resulting 2DEG sheet densities in these heterostructures are calculated and compared to those occurring at AlGaN/GaN interfaces. The combined effect of the strong polarization-induced bound charges and the large conduction band offsets at the AlScN/GaN and AlYN/GaN heterojunctions results in the formation of 2DEGs with very high electron sheet densities.about 4 … 5 times as large as those in Al0.3Ga0.7N/GaN. Our results demonstrate the potential of AlScN and AlYN barriers for GaN-based high electron mobility transistors.Die physikalischen Eigenschaften des Galliumnitrid (GaN) und der darauf basierenden Materialien eignen sich besonders zur Herstellung von leistungselektronischen Bauelementen. Die große Bandlücke und hohe elektrische Durchbruchfeldstärke von GaN in Kombination mit einem zweidimensionalen Elektronengas hoher Dichte durch induzierte Polarisation in der AlGaN/GaN-Grenzfläche ermöglicht die Entwicklung von Transistoren mit hohen Sperrspannungen, niedrigen Durchlasswiderständen und niedrigen Schaltladungen. Die aus herkömmlichen GaN-HEMTs hergestellten Transistoren haben jedoch bereits ihre Leistungsgrenze erreicht. Um die zukünftigen Bedürfnisse von leistungselektronischen Bauelementen zu erfüllen, werden Forschungen zu nichtklassischen HEMT-Konzepten, zum Beispiel Superjunction GaN-HEMT, PNT GaN-HEMTs oder zu neuartigen Barrierematerialien durchgeführt. Diese Arbeit will die GaN-Technologie durch neue Ansätze in Design und Charakterisierung hocheffizienter GaN-Transistoren vorantreiben, um ihr volles Potential zu entfalten. Das Ziel der vorliegenden Arbeit ist es, verschiedene nichtklassische GaN HEMT-Konzepte hinsichtlich ihrer Performance sowie ihrer Eignung für zukünftige Logik, leistungselektronisch und RF Anwendungen zu bewerten und ihren Designspielraum einzugrenzen. Die Untersuchungen basieren auf numerischen Bauelementesimulationen unter Zuhilfenahme analytischer Berechnungen. Es wird gezeigt, dass das einfache und robuste Drift-Diffusionsmodell für die Simulation solcher nichtklassischen Bauelemente geeignet ist. Die Koexistenz von zweidimensionalen Elektronen- und Löchergasen in GaN-basierten Heterostrukturen wird mittels analytischer Modelle, die im Rahmen dieser Arbeit entwickelt wurden, und selbstkonsistenten numerischen Lösungen der Schrödinger- und Poisson-Gleichungen untersucht. Es kann gezeigt werden, dass für bestimmte Kombinationen von Bias-Bedingungen und Schichtdesign koexistierende 2DEGs und 2DHGs in GaN/AlGaN/GaN-Strukturen gebildet werden können, wobei sich das 2DHG an der Grenzfläche zwischen Grenzfläche und Grenzfläche befindet. Sobald ein 2DHG erzeugt ist, nimmt der Effekt der Gate-Spannung auf das 2DEG schnell ab und eine Sättigung der 2DEG-Dichte wird beobachtet. Außerdem ist es in Strukturen mit dünnen Barrieren viel schwieriger, ein 2DHG selbst für große Oberflächenpotentiale zu erzeugen. Die Formierung eines zweiten Kanals in AlGaN/GaN/AlGaN/GaN Heterostrukturen wurde untersucht. Es wurde gezeigt, dass für bestimmte Kombinationen von Bias-Bedingungen und Schichtdesign koexistierende zwei Kanäle in AlGaN2/GaN2/AlGaN1/GaN1-Strukturen gebildet werden können, wobei sich beide Kanäle am AlGaN1/GaN1 und AlGaN2/GaN2 befinden. Sobald der zweite Kanal erzeugt ist, nimmt die Wirkung der Gate-Spannung auf das erste 2DEG schnell ab und eine Sättigung des Drain-Stroms wird beobachtet. Besondere Aufmerksamkeit wurde auf einen neuartigen Inverter mit vertikalem Aufbauen gelegt, indem diese zwei Kanäle verwendet wurden. Andererseits konzentrieren sich theoretische Untersuchungen von AlGaN/GaN-HEMT-Strukturen für leistungselektronische Anwendungen auf die Abschätzung von Oxidgrenzflächenladungen in MIS-HEMT-Strukturen, und es werden zwei Simulationsstudien zu alternativen selbstsperrenden HEMT-Konzepten vorgestellt. Die Untersuchung von Oxidgrenzflächenladungen basiert auf einem Vergleich von gemessenen und simulierten Schwellenspannungen experimenteller HEMTs mit und ohne Al2O3-Schicht unter dem Gate. Wir finden, dass in beiden Fällen die geschätzte Oxidgrenzflächenladung die gleiche ist. Darüber hinaus entwickelten wir ein einfaches analytisches Schwellenspannungsmodell für die MIS HEMT Struktur, mit dem die Grenzflächenladung mit einem Taschenrechner abgeschätzt werden kann. Wir schlagen auch einen neuen Ansatz vor, bei dem die Wirkung einer p-dotierten Deckschicht mit der eines Gateoxids kombiniert wird, um einen selbstsperrenden HEMT zu erreichen. Wir konzentrieren uns auf die von Ota et al. mit 1D-Schrödinger-Poisson-Simulationen. Insbesondere zeigt unser analytisches Modell, dass die Schwellenspannung unabhängig von der Dicke sowohl der PNT-Schicht als auch der gespannten GaN-Kanalschicht ist. Darüber hinaus diskutieren wir Optionen zur Erhöhung der Elektronendichte in den ungesteuerten (ungated) Bauelementbereichen, um die Source/Drain-Widerstände zu reduzieren. Darüber hinaus werden gated kubische InGaN/InN-Heterostrukturen für die Anwendung in InN-basierten Transistoren mit hoher Elektronenmobilität theoretisch untersucht. Die Bildung zweidimensionaler Trägergase in InGaN/InN-Strukturen wird im Detail untersucht und Designprobleme für die InGaN-Barriere untersucht. Es wird gezeigt, dass für bestimmte Oberflächenpotentiale eine unerwünschte Sättigung der Schichtdichte des Elektronengases in der InN-Kanalschicht auftreten kann. Optionen zur Verbesserung der Elektronendichte in den Kanal- und Oberflächenpotentialbereichen für einen geeigneten Transistorbetrieb werden vorgestellt. Abschließend wird die Bildung zweidimensionaler Elektronengase (2DEGs) in gitterangepassten AlScN/GaN- und AlYN/GaN-Heterostrukturen durch numerische selbstkonsistente Lösungen der Schrödinger- und Poisson-Gleichungen untersucht. Die Elektronenkonzentrationsprofile und die resultierenden 2DEG-Schichtdichten in diesen Heterostrukturen werden berechnet und mit denen verglichen, die an AlGaN/GaN-Grenzflächen auftreten. Die kombinierte Wirkung der stark polarisationsinduzierten gebundenen Ladungen und der großen Leitungsbandoffsets an den AlScN/GaN- und AlYN/GaN-Heteroübergängen führt zur Bildung von 2DEGs mit sehr hohen Elektronendichtedichten. Für die AlScN/GaN- und AlYN/GaN-Heterostrukturen werden 2DEG-Schichtdichten von etwa 4 bis 5-mal so groß wie für Al0,3Ga0,7N/GaN-Strukturen berechnet. Unsere Ergebnisse demonstrieren das Potenzial von AlScN- und AlYN-Barrieren für GaN-basierte Transistoren mit hoher Elektronenmobilität