Accelerating Electromigration Aging: Fast Failure Detection for Nanometer ICs

For practical testing and detection of electromigration (EM) induced failures in dual damascene copper interconnects, one critical issue is creating stressing conditions to induce the chip to fail exclusively under EM in a very short period of time so that EM sign-off and validation can be carried out efficiently. Existing acceleration techniques, which rely on increasing temperature and current densities beyond the known limits, also accelerate other reliability effects making it very difficult, if not impossible, to test EM in isolation. In this article, we propose novel EM wear-out acceleration techniques to address the aforementioned issue. First we show that multi-segment interconnects with reservoir and sink structures can be exploited to significantly speedup the EM wear-out process. Based on this observation, we propose three strategies to accelerate EM induced failure: reservoir-enhanced acceleration, sink-enhanced acceleration, and a hybrid method that combines both reservoir and sink structures. We then propose several configurable interconnect structures that exploit atomic reservoirs and sinks for accelerated EM testing. Such configurable interconnect structures are very flexible and can be used to achieve significant lifetime reductions at the cost of some routing resources. Using the proposed technique, EM testing can be carried out at nominal current densities, and at a much lower temperature compared to traditional testing methods. This is the most significant contribution of this work since, to our knowledge, this is the only method that allows EM testing to be performed in a controlled environment without the risk of invoking other reliability effects that are also accelerated by elevated temperature and current density. Simulation results show that, using the proposed method, we can reduce the EM lifetime of a chip from 10 years down to a few hours 10^5X acceleration under the 150C temperature limit, which is sufficient for practical EM testing of typical nanometer CMOS ICs

Performance and Reliability of Integrated Solar Thermal Electronics and Devices

The performance and reliability of solar thermal electrical device is studied. A

Investigation of the Fundamental Reliability Unit for Cu Dual-Damascene Metallization

An investigation has been carried out to determine the fundamental reliability unit of copper dual-damascene metallization. Electromigration experiments have been carried out on straight via-to-via interconnects in the lower metal (M1) and the upper metal (M2), and in a simple interconnect tree structure consisting of straight via-to-via line with an extra via in the middle of the line (a "dotted-I"). Multiple failure mechanisms have been observed during electromigration testing of via-to-via Cu interconnects. The failure times of the M2 test structures are significantly longer than that of identical M1 structures. It is proposed that this asymmetry is the result of a difference in the location of void formation and growth, which is believed to be related to the ease of electromigration-induced void nucleation and growth at the Cu/Si₃N₄ interface. However, voids were also detected in the vias instead of in the Cu lines for some cases of early failure of the test lines. These early failures are suspected to be related to the integrity and reliability of the Cu via. Different magnitudes and directions of electrical current were applied independently in two segments of the interconnect tree structure. As with Al-based interconnects, the reliability of a segment in this tree strongly depends on the stress conditions of the connected segment. Beyond this, there are important differences in the results obtained under similar test conditions for Al-based and Cu-based interconnect trees. These differences are thought to be associated with variations in the architectural schemes of the two metallizations. The absence of a conducting electromigration-resistant overlayer in Cu technology allows smaller voids to cause failure in Cu compared to Al. Moreover, the Si₃N₄ overlayer that serves as an interlevel diffusion barrier provides sites for easy nucleation of voids and also provides a high diffusivity path for electromigration. The results reported here suggest that while segments are not the fundamental reliability unit for circuit-level reliability assessments for Al or Cu, vias, rather than trees, might be the appropriate fundamental units for the assessment of Cu reliability.Singapore-MIT Alliance (SMA

Simulation for Reliability, Hardware Security, and Ising Computing in VLSI Chip Design

The continued scaling of VLSI circuits has provided a wealth of opportunities andchallenges to the VLSI circuit design area. Both these challenges and opportunities, however,require new simulation tools that can enable their solution or exploitation as classicalmethods typically dealt with problem domains with smaller scales or less complexity. Inthis dissertation, simulation methods are presented to address the emerging VLSI designtopics of Electromigration induced aging and Ising computing and are then applied to theapplication areas of hardware security and graph partitioning respectively.The Electromigration aging effect in VLSI circuits is a long-term reliability issueaffecting current carrying metal wires leading to IR drop degradation. Typically, simpleanalytical equations can determine a wire’s effective age or if it will be affected by the EMaging effect at all. However, these classical methods are overly conservative and can lead toover design or unnecessary design iterations. Furthermore, it is expected that the EM agingeffect will become more severe in future Integrated Cirucits (ICs) due to increasing currentdensities and the prevalance of polycrystaline copper atom structures seen at small wiredimensions. For this reason, more comprehensive simulation techniques that can efficientlysimulate the EM effect with less conservative results can help mitigate overdesign andincrease design margins while reducing design iterations.The area of Hardware Security is becoming increasingly important as the chipsupply chain becomes more globalized and the integrity of chips becomes more diffiuclt toverify. Utilizing the accurate simulation techniques for EM, we can utilize this reliabilityeffect to demonstrate how a reliability based attack could be perpatrated. Furthermore, wecan utilize this aging effect as a defense mechanism to help us validate the integrity of anIC and detect counterfeit chips in the component supply chain market.Ising computing is an emerging method of solving combinatorial optimization problemsby simulating the interactions of so-called spin glasses and their interactions. Borrowingconcepts from quantum computing, this methods mimics the quantum interaction betweenspin glasses in such a way that finding a ground state of these spin glass models leadsto the solution of a particular problem. In this dissertation, effective methods of simulatingthe spin glass interactions using General Purpose Graphics Processing Units (GPGPUs)and finding their ground state are developed.In addition to the GPU based Ising model simulations, important combinatorialproblems can be mapped to the Ising model. In this dissertation the Ising solver is appliedto graph partitioning which can be utilized in VLSI design and many other domains as well.Specifically, solvers for the maxcut problem and the balanced min-cut partitioning problemare developed

Scaling and process effect on electromigration reliability for Cu/low k interconnects

textThe microelectronics industry has been managing the RC delay problem arising from aggressive line scaling, by replacing aluminum (Al) by copper (Cu) and oxide dielectric by low-k dielectric. Electromigration (EM) turned out to be a serious reliability problem for Cu interconnects due to the implementation of mechanically weaker low-k dielectrics. In addition, line width and via size scaling resulted in the need of a novel diffusion barrier, which should be uniform and thin. The objective of this dissertation is to investigate the impacts of Ta barrier process, such as barrier-first and pre-clean first, and scaling of barrier and line/via on EM reliability of Cu/low-k interconnects. For this purpose, EM statistical test structures, having different number of line segments, line width, and via width, were designed. The EM test structures were fabricated by a dualdamascene process with two metal layers (M1/Via/M2), which were then packaged for EM tests. The package-level EM tests were performed in a specially designed vacuum chamber with pure nitrogen environment. The novel barrier deposition process, called barrier-first, showed a higher (jL)[subscript c] product and prolonged EM lifetime, compared with the conventional Ta barrier deposition process, known as pre-clean first. This can be attributed to the improved uniformity and thickness of the Ta layer on the via and trench, as confirmed by TEM. As for the barrier thickness effect, the (jL)c product decreased with decreasing thickness, due to reduced Cu confinement. A direct correlation between via size and EM reliability was found; namely, EM lifetime and statistics degraded with via size. This can be attributed to the fact that critical void length to cause open circuit is about the size of via width. To investigate further line scaling effect on EM reliability, SiON (siliconoxynitride) trenchfilling process was introduced to fabricate 60-nm lines, corresponding to 45-nm technology, using a conventional, wider line lithograph technology. The EM lifetime of 60-nm fine lines with SiON filling was longer than that of a standard damascene structure, which can be attributed to a distinct via/metal-1 configuration in reducing process-induced defects at the via/metal-1 interface.Materials Science and Engineerin

Physics-Based Electromigration Modeling and Analysis and Optimization

Long-term reliability is a major concern in modern VLSI design. Literature has shown that reliability gets worse as technology advances. It is expected that the future VLSI systems would have shorter reliability-induced lifetime comparing with previous generations. Being one of the most serious reliability effects, electromigration (EM) is a physical phenomenon of the migration of metal atoms due to the momentum exchange between atoms and the conducting electrons. It can cause wire resistance change or open circuit and result in functional failure of the circuit. Power-ground networks are the most vulnerable part to EM effect among all the interconnect wires since the current flow on this part is the largest on the chip. With new generation oftechnology node and aggressive design strategies, more accurate and efficient EM models are required. However, traditional EM approaches are very conservative and cannot meet current aggressive design strategies. Besides circuit level, EM also need to be thoroughly studied in system level due to limited power and temperature budgets among cores on chip. This research focuses on developing physical level EM model for VLSI circuits and system level EM optimization for multi-core systems in order to overcome the aforementioned problems. Specifically, for physical level, we develop two EM immortality check methods and a power grid EM check method. Firstly, a voltage based EM immortality analysis has been developed. Immortality condition in nucleation phase can be determined fast and accurately for multi-segment interconnect wires. Secondly, a saturation volume based incubation phase immortality check method has been proposed. This method can further reduce the redundancy in VLSI circuit design by immortality check in multiphase. Furthermore, both immortality check methods are integrated into a new power grid EM check methodology (EMspice) as filter for EM analysis. These filters can accelerate the simulation by filtering out immortal trees so that we only need to do simulation on fewer trees that are mortal. Coupled EM simulation considering both hydrostatic stress and electronic current/voltage in the power grid network will be applied to these mortal trees. This tool can work seamlessly with commercial synthesis flow. Besides physical level reliability models, system level reliability optimization is also discussed in this research. A deep reinforcement learning based EM optimization has been proposed for multi-core system. Both long term reliability effect (hard error) and transient soft error are considered. Energy can be optimized with all the reliability and other constraints fast and accurately compared to existing reliability management techniques. Last but not least, a scheduling based reliability optimization method for multi-core systems has been proposed. NBTI, HCI and EM are considered jointly. Lifetime of the system can be improved significantly compared to traditional methods which mainly focus on utilization

Fast thermal cycling-enhanced electromigration in power metallization

Multilevel interconnects used in power ICs are susceptible to short circuit failure due to a combination of fast thermal cycling and electromigration stresses. In this paper, we present a study of electromigration-induced extrusion short-circuit failure in a standard two level metallization currently used in power ICs and in particular the effect of fast thermal cycling on the subsequent electromigration lifetime. A special test chip was designed, in which the electromigration test structure is integrated with a heating element and a diode as temperature sensor in order to generate fast temperature swings and to monitor them. Experimental results showed that with the introduction of fast thermal cycling as a preconditioning, the electromigration lifetime is significantly reduced. We observed that the reduction of the electromigration lifetime depends on the stress time, temperature range and the minimum temperature. Electromigration simulations using a two-dimensional simulator confirm the extrusion short circuit as failure mechanism

Effects of mechanical properties on the reliability of Cu/low-k metallization systems

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references (leaves 211-217).Cu and low-dielectric-constant (k) metallization schemes are critical for improved performance of integrated circuits. However, low elastic moduli, a characteristic of the low-k materials, lead to significant reliability degradation in Cu-interconnects. A thorough understanding of the effects of mechanical properties on electromigration induced failures is required for accurate reliability assessments. During electromigration inside Cu-interconnects, a change in atomic concentration correlates with a change in stress through the effective bulk modulus of the materials system, B, which decreases as the moduli of low-k materials used as inter-level dielectrics (ILDs) decrease. This property is at the core of discussions on electromigration-induced failures by all mechanisms. B is computed using finite element modeling analyses, using experimentally determined mechanical properties of the individual constituents. Characterization techniques include nanoindentation, cantilever deflection, and pressurized membrane deflection for elastic properties measurements, and chevron-notched double-cantilever pull structures for adhesion measurements. The dominant diffusion path in Cu-interconnects is the interface between Cu and the capping layer, which is currently a Si3N4-based film. We performed experiments on Cu-interconnect segments to investigate the kinetics of electromigration. A steady resistance increase over time prior to open-circuit failure, a result of void growth, correlates with the electromigration drift velocity. Diffusive measurements made in this fashion are more fundamental than lifetime measurements alone, and correlate with the combined effects of the electron wind and the back stress forces during electromigration induced void growth.(cont.)Using this method, the electromigration activation energy was determined to be 0.80±0.06eV. We conducted experiments using Cu-interconnects with different lengths to study line length effects. Although a reliability improvement is observed as the segment length decreases, there is no deterministic current-density line-length product, jL, for which all segments are immortal. This is because small, slit-like voids forming directly below vias will cause open-failures in Cu-interconnects. Therefore, the probabilistic jLcrit values obtained from via-above type nterconnects approximate the thresholds for void nucleation. The fact that jLcrit,nuc monotonically decreases with B results from an energy balance between the strain energy released and surface energy cost for void nucleation and the critical stress required for void nucleation is proportional to B. We also performed electromigration experiments using Cu/low-k interconnect trees to investigate the effects of active atomic sinks and reservoirs on interconnect reliability. In all cases, failures were due to void growth. Kinetic parameters were extracted to be ... Quantitative analysis demonstrates that the reliability of the failing segments is modulated by the evolution of stress in the whole interconnect tree. During this process, not only the diffusive parameters but also B play critical roles. However, as B decreases, the positive effects of reservoirs on reliability are diminished, while the negative effects of sinks on reliability are amplified.(cont.) Through comprehensive failure analyses, we also successfully identified the mechanism of electromigration-induced extrusions in Cu/low-k interconnects to be nearmode-I interfacial fracture between the Si3N4-based capping layer and the metallization/ILD layer below. The critical stress required for extrusion is found to depend not only on B but also on the layout and dimensions of the interconnects. As B decreases, sparsely packed, wide interconnects are most prone to extrusion-induced failures. Altogether, this research accounts for the effects of mechanical properties on all mechanisms of failure due to electromigration. The results provide an improved experimental basis for accurate circuit-level, layout-specific reliability assessments.by Frank LiLi Wei.Ph.D

New methodologies for interconnect reliability assessments of integrated circuits

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2000.Includes bibliographical references (leaves 245-251).The stringent performance and reliability demands that will accompany the development of next-generation circuits and new metallization technologies will require new and more accurate means of assessing interconnect reliability. Reliability assessments based on conventional methodologies are flawed in a number of very important ways, including the disregard of the effects of complex interconnect geometries on reliability. New models, simulations and experimental methodologies are required for the development of tools for circuit-level and process-sensitive reliability assessments. Most modeling and experimental characterization of interconnect reliability has focused on simple straight lines terminating at pads or vias. However, laid-out integrated circuits usually have many interconnects with junctions and wide-to-narrow transitions. In carrying out circuit-level reliability assessments it is important to be able to assess the reliability of these more complex shapes, generally referred to as "trees". An interconnect tree consists of continuously connected high-conductivity metal within one layer of metallization. Trees terminate at diffusion barriers at vias and contacts, and, in the general case, can have more than one terminating branch when the tree includes junctions. We have extended the understanding of "immortality" demonstrated and analyzed for straight stud-to-stud lines, to trees of arbitrary complexity. We verified the concept of immortality in interconnect trees through experiments on simple tree structures. This leads to a hierarchical approach for identifying immortal trees for specific circuit layouts and models for operation. We suggest a computationally efficient and flexible strategy for assessment of the reliability of entire integrated circuits. The proposed hierarchical reliability analysis can provide reliability assessments during the design and layout process (Reliability Computer Aided Design, RCAD). Design rules are suggested based on calculations of the electromigration-induced development of inhomogeneous steadystate mechanical stress states. Failure of interconnects by void nucleation in single-layermetallization, as well as failure by void growth in the presence of refractory metal shunt layers are taken into account. The proposed methodology identifies a large fraction of interconnect trees in a typical design as immune to electromigration-induced failure. To complete a circuit-level-reliability analysis, it is also necessary to estimate the lifetimes of the mortal trees. We have developed simulation tools that allow modeling of stress evolution and failure in arbitrarily complex trees. We have demonstrated the validity of these models and simulations through comparisons with experiments on simple trees, such as "L"- and "T"-shaped trees with different current configurations. Because analyses made using simulations are computationally intensive, simulations should be used for analysis of the least reliable trees. The reliability of the majority of the mortal trees can be assessed using a conservative default model based on nodal reliability analyses for the assessment of electromigration-limited reliability of interconnect trees. The lifetimes of the nodes are calculated by estimating the times for void nucleation, void growth to failure, and formation of extrusions. The differences between straight stud-to-stud lines and interconnect trees are studied by investigating the effects of passive and active reservoirs on electromigration. Models and simulations were validated through comparisons with experiments on simple tree structures, such as lines broken into two limbs with different currents in each limb. Models, simulations and experimental results on the reliability of interconnect trees are shown to yield mutually consistent results. Taken together, the results from this research have provided the basis for the development of the first RCAD tool capable of accurate circuit-level, processing sensitive and layout-specific reliability analyses.by Stefan P. Hau-Riege.Ph.D