Methods and Results of Power Cycling Tests for Semiconductor Power Devices

This work intends to enhance the state of the research in power cycling tests with statements on achievable measurement accuracy, proposed test bench topologies and recommendations on improved test strategies for various types of semiconductor power devices. Chapters 1 and 2 describe the current state of the power cycling tests in the context of design for reliability comprising applicable standards and lifetime models. Measurement methods in power cycling tests for the essential physical parameters are explained in chapter 3. The dynamic and static measurement accuracy of voltage, current and temperature are discussed. The feasibly achievable measurement delay tmd of the maximal junction temperature Tjmax, its consequences on accuracy and methods to extrapolate to the time point of the turn-off event are explained. A method to characterize the thermal path of devices to the heatsink via measurements of the thermal impedance Zth is explained. Test bench topologies starting from standard setups, single to multi leg DC benches are discussed in chapter 4. Three application-closer setups implemented by the author are explained. For tests on thyristors a test concept with truncated sinusoidal current waveforms and online temperature measurement is introduced. An inverter-like topology with actively switching IGBTs is presented. In contrast to standard setups, there the devices under test prove switching capability until reaching the end-of-life criteria. Finally, a high frequency switching topology with low DC-link voltage and switching losses contributing significantly to the overall power losses is presented providing new degrees of freedom for setting test conditions. The particularities of semiconductor power devices in power cycling tests are thematized in chapter 5. The first part describes standard packages and addressed failure mechanisms in power cycling. For all relevant power electronic devices in silicon and silicon carbide, the devices’ characteristics, methods for power cycling and their consequences for test results are explained. The work is concluded and suggestions for future work are given in chapter 6.:Abstract 1 Kurzfassung 3 Acknowledgements 5 Nomenclature 10 Abbreviations 10 Symbols 12 1 Introduction 19 2 Applicable Standards and Lifetime Models 25 3 Measurement parameters in power cycling tests 53 4 Test Bench Topologies 121 5 Semiconductor Power Devices in Power Cycling 158 6 Conclusion and Outlook 229 References 235 List of Publications 253 Theses 257Diese Arbeit bereichert den Stand der Wissenschaft auf dem Gebiet von Lastwechseltests mit Beiträgen zu verbesserter Messgenauigkeit, vorgeschlagenen Teststandstopologien und verbesserten Teststrategien für verschiedene Arten von leistungselektronischen Bauelementen. Kurzgefasst der Methodik von Lastwechseltests. Das erste Themengebiet in Kapitel 1 und Kapitel 2 beschreibt den aktuellen Stand zu Lastwechseltests im Kontext von Design für Zuverlässigkeit, welcher in anzuwendenden Standards und publizierten Lebensdauermodellen dokumentiert ist. Messmethoden für relevante physikalische Parameter in Lastwechseltests sind in Kapitel 3. erläutert. Zunächst werden dynamische und statische Messgenauigkeit für Spannung, Strom und Temperaturen diskutiert. Die tatsächlich erreichbare Messverzögerung tMD der maximalen Sperrschichttemperatur Tjmax und deren Auswirkung auf die Messgenauigkeit der Lastwechselfestigkeit wird dargelegt. Danach werden Methoden zur Rückextrapolation zum Zeitpunkt des Abschaltvorgangs des Laststroms diskutiert. Schließlich wird die Charakterisierung des Wärmepfads vom Bauelement zur Wärmesenke mittels Messung der thermischen Impedanz Zth behandelt. In Kapitel 4 werden Teststandstopologien beginnend mit standardmäßig genutzten ein- und mehrsträngigen DC-Testständen vorgestellt. Drei vom Autor umgesetzte anwendungsnahe Topologien werden erklärt. Für Tests mit Thyristoren wird ein Testkonzept mit angeschnittenem sinusförmigem Strom und in situ Messung der Sperrschichttemperatur eingeführt. Eine umrichterähnliche Topologie mit aktiv schaltenden IGBTs wird vorgestellt. Zuletzt wird eine Topologie mit hoch frequent schaltenden Prüflingen an niedriger Gleichspannung bei der Schaltverluste signifikant zur Erwärmung der Prüflinge beitragen vorgestellt. Dies ermöglicht neue Freiheitsgrade um Testbedingungen zu wählen. Die Besonderheiten von leistungselektronischen Bauelementen werden in Kapitel 5 thematisiert. Der erste Teil beschreibt Gehäusetypen und adressierte Fehlermechanismen in Lastwechseltests. Für alle untersuchten Bauelementtypen in Silizium und Siliziumkarbid werden Charakteristiken, empfohlene Methoden für Lastwechseltests und Einflüsse auf Testergebnisse erklärt. Die Arbeit wird in Kapitel 6 zusammengefasst und Vorschläge zu künftigen Arbeiten werden unterbreitet.:Abstract 1 Kurzfassung 3 Acknowledgements 5 Nomenclature 10 Abbreviations 10 Symbols 12 1 Introduction 19 2 Applicable Standards and Lifetime Models 25 3 Measurement parameters in power cycling tests 53 4 Test Bench Topologies 121 5 Semiconductor Power Devices in Power Cycling 158 6 Conclusion and Outlook 229 References 235 List of Publications 253 Theses 25

ISPET: Interface Sintering Process Enhanced Technology

The research presented in this thesis was carried out in VISHAY Semiconductor Italiana S.P.A. at Borgaro Torinese - Italy. The framework of this thesis is the study of new materials for power electronics application, analysing their thermal, mechanical and electrical properties. Emerging application of high power systems requires new methods for power electronics integration and packaging. Stringent requirements in size and weight, reliability, durability, ambient and operation temperatures are pushing to go beyond the limits in industrial applications. As a consequence, our studies are focused on power modules, incorporating new materials and technology processes (sintering) for dies or chips (silicon), substrates and interconnection materials (wire bonding). This thesis work starts introducing the power semiconductor devices used in power electronics and their integration on Power Integrated Circuits (low and medium power density) and Power Modules (medium, high and very high power density). This chapter will explain technology evolution, power semiconductor device utilization mode and some applications. Chapter 2 will be focused on power modules packages. They have an important role for providing cooling, electrical connection and correct insulation, between the internal semiconductor devices and the external circuit. Isolated and non isolated packages are analysed and compared. Chapter 3 will make a point on the methods of thermal characterization and reliability tests, that were implemented to evaluate the impact of the introduction of new materials and processes into the device. In chapter 4, first experimental results, related to the sintering process will be discussed. In this chapter the attention will be focused on the Chip to substrate Joint of the device, analysing methods to mechanically fix die to substrate. The sintering process will be treated, analysing the process and the results will be thermally and mechanically characterized. The chapter 5 will present the experimental part oriented to the combinations of materials to produce a better heavy wire bonding, supported by a Design of Experiments (DOE). The behaviour of didifferent wires will be compared through thermal characterization methods and reliability test

Microstructural Response of Highly Porous Sintered Nano-silver Particle Die Attachments to Thermomechanical Cycling

This paper deals with the performance of sintered nano-silver bonds used as wide-bandgap power module die attachment technology. The paper specifically explores the fine-scale microstructures of highly porous sintered attachments under power cycling to provide a deeper understanding of the significance of porosity as a reliability-related microstructural parameter. Attachments prepared at 220°C using a pressure of 6 MPa for 1 s (parameters known to generate approximately 50% porosity from previous work) and subsequently subjected to 650,000 power cycles between 50°C and 200°C are assessed. A correlative workflow integrating x-ray computed tomography, focused ion beam (FIB) and electron backscatter diffraction (EBSD) data is applied to merge meso- and nanoscale microstructural features to illuminate the degradation mechanisms. The as-sintered Ag layer has a high volume of heterogeneously distributed pores, and consists of randomly oriented equiaxed grains whose sizes vary depending on the local density of the region sampled. Power cycling promotes grain growth and the loss of twin boundaries, and these changes are more pronounced within more dense regions of the Ag attachment. In contrast, the copper substrate appears to undergo some grain refinement, with deformation twins visible within finer-grained zones during power cycling. Cracks, which appear to start off within the Ag layer, propagate across the Ag-Cu boundary and transgranularly through fine-grained regions within the copper with little tortuosity. These observations are discussed within the context of reliability behaviour

Analysis of the degradation mechanisms occurring in the topside interconnections of IGBT power devices during power cycling

29th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, ESREF 2018, AALBORG, DANEMARK, 01-/10/2018 - 05/10/2018This paper presents an experimental technique to characterize the damage evolution of the topside interconnections of power semi-conductor devices during power cycling tests. DC power cycling tests are done on Semikron SKIM 63 power modules, a solder-free module with silver sintered chips, ensuring the degradations to appear in the top layers only. The cycled substrates are then extracted from the test bench at different steps of the aging for analysis. Four-probe measurements are implemented on the chips so that the evolution of physical parameters representative of the degradation in the metallization and the bond wire contacts can be obtained. Finally, optical microscopy analysis of cross-sections at the wire bond contact interface is carried out to corroborate the electrical measurements to the crack length growth after specific aging intervals

Innovation: Key to the future

The NASA Marshall Space Flight Center Annual Report is presented. A description of research and development projects is included. Topics covered include: space science; space systems; transportation systems; astronomy and astrophysics; earth sciences; solar terrestrial physics; microgravity science; diagnostic and inspection system; information, electronic, and optical systems; materials and manufacturing; propulsion; and structures and dynamics