Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Efficient DSP and Circuit Architectures for Massive MIMO: State-of-the-Art and Future Directions

Massive MIMO is a compelling wireless access concept that relies on the use of an excess number of base-station antennas, relative to the number of active terminals. This technology is a main component of 5G New Radio (NR) and addresses all important requirements of future wireless standards: a great capacity increase, the support of many simultaneous users, and improvement in energy efficiency. Massive MIMO requires the simultaneous processing of signals from many antenna chains, and computational operations on large matrices. The complexity of the digital processing has been viewed as a fundamental obstacle to the feasibility of Massive MIMO in the past. Recent advances on system-algorithm-hardware co-design have led to extremely energy-efficient implementations. These exploit opportunities in deeply-scaled silicon technologies and perform partly distributed processing to cope with the bottlenecks encountered in the interconnection of many signals. For example, prototype ASIC implementations have demonstrated zero-forcing precoding in real time at a 55 mW power consumption (20 MHz bandwidth, 128 antennas, multiplexing of 8 terminals). Coarse and even error-prone digital processing in the antenna paths permits a reduction of consumption with a factor of 2 to 5. This article summarizes the fundamental technical contributions to efficient digital signal processing for Massive MIMO. The opportunities and constraints on operating on low-complexity RF and analog hardware chains are clarified. It illustrates how terminals can benefit from improved energy efficiency. The status of technology and real-life prototypes discussed. Open challenges and directions for future research are suggested.Comment: submitted to IEEE transactions on signal processin

Static and dynamic nonlinearity compensation techniques for high performance current-steering digital-to-analog converters

High-speed high-accuracy digital-to-analog converters (DACs) are the crucial building blocks for many signal processing and telecommunication systems. The current-steering architecture is extensively used for these applications. With different decoding schemes--binary-weighted, unary-coded, and segment-coded, current-steering DACs are realized by groups of matched current sources. Their performance is limited by many nonlinear mechanisms such as random mismatch errors, gradient effect, code and voltage dependence of finite output impedance, nonlinear settling time, charge injection, and switch timing errors. In this thesis, two nonlinearity compensation techniques are presented to improve the overall performance of the current-steering DACs. The first design technique is a novel digital calibration technique--complete-folding, which effectively compensates the random mismatch errors by selectively regrouping current sources into a fully binary-weighted array based on current comparisons after chip fabrication. The implementation only requires an analog current comparator and some digital circuitry. The minimum requirement of analog circuits makes complete-folding calibration suitable for DAC design in the low-voltage process. Statistical results with a behavioral model of a 14-bit segmented DAC in MATLAB show that complete-folding calibration can reduce the total gate area of current sources by a factor of almost 1200 compared to the DAC without using any calibration. Additional results also show that this new calibration technique has the superior performance in compensating random mismatch errors as compared to state-of-the-art. The second design technique is a novel output impedance linearization technique that very effectively reduces the code and voltage dependence of finite output impedance. The linearization is achieved by using a small DAC switched with control signals opposite to those for the main DAC. The area and power overhead is less than 5% of the main DAC. Simulation results with a 14-bit segmented current-steering DAC in standard 0.18μm CMOS process show that the DAC\u27s integral nonlinearity (INL) due to finite output impedance is improved by almost 5 bits. Additional results show that this technique is very robust to random mismatch errors. Moreover, not only the static linearity is improved, but most importantly there is a large dynamic linearity enhancement by output impedance linearization. Simulation results show that spurious-free dynamic range (SFDR) can be improved by almost 30 dB at the low signal frequencies and more than 8 dB for the high signal frequencies up to Nyquist rate while sampling at 500MS/s

Electronic integration of the uk-1 international ionosphere satellite

Electronic integration of international ionosphere satellit

Analysis And Simulation Tools For Solar Array Power Systems

This dissertation presents simulation tools developed specifically for the design of solar array power systems. Contributions are made in several aspects of the system design phases, including solar source modeling, system simulation, and controller verification. A tool to automate the study of solar array configurations using general purpose circuit simulators has been developed based on the modeling of individual solar cells. Hierarchical structure of solar cell elements, including semiconductor properties, allows simulation of electrical properties as well as the evaluation of the impact of environmental conditions. A second developed tool provides a co-simulation platform with the capability to verify the performance of an actual digital controller implemented in programmable hardware such as a DSP processor, while the entire solar array including the DC-DC power converter is modeled in software algorithms running on a computer. This virtual plant allows developing and debugging code for the digital controller, and also to improve the control algorithm. One important task in solar arrays is to track the maximum power point on the array in order to maximize the power that can be delivered. Digital controllers implemented with programmable processors are particularly attractive for this task because sophisticated tracking algorithms can be implemented and revised when needed to optimize their performance. The proposed co-simulation tools are thus very valuable in developing and optimizing the control algorithm, before the system is built. Examples that demonstrate the effectiveness of the proposed methodologies are presented. The proposed simulation tools are also valuable in the design of multi-channel arrays. In the specific system that we have designed and tested, the control algorithm is implemented on a single digital signal processor. In each of the channels the maximum power point is tracked individually. In the prototype we built, off-the-shelf commercial DC-DC converters were utilized. At the end, the overall performance of the entire system was evaluated using solar array simulators capable of simulating various I-V characteristics, and also by using an electronic load. Experimental results are presented

Digital-to-Analog Converter Interface for Computer Assisted Biologically Inspired Systems

In today\u27s integrated circuit technology, system interfaces play an important role of enabling fast, reliable data communications. A key feature of this work is the exploration and development of ultra-low power data converters. Data converters are present in some form in almost all mixed-signal systems; in particular, digital-to-analog converters present the opportunity for digitally controlled analog signal sources. Such signal sources are used in a variety of applications such as neuromorphic systems and analog signal processing. Multi-dimensional systems, such as biologically inspired neuromorphic systems, require vectors of analog signals. To use a microprocessor to control these analog systems, we must ultimately convert the digital control signal to an analog control signal and deliver it to the system. Integrating such capabilities of a converter on chip can yield significant power and chip area constraints. Special attention is paid to the power efficiency of the data converter, the data converter design discussed in this thesis yields the lowest power consumption to date. The need for a converter with these properties leads us to the concept of a scalable array of power-efficient digital-to-analog converters; the channels of which are time-domain multiplexed so that chip-area is minimized while preserving performance. To take further advantage of microprocessor capabilities, an analog-to- digital design is proposed to return the analog system\u27s outputs to the microprocessor in a digital form. A current-steering digital-to-analog converter was chosen as a candidate for the conversion process because of its natural speed and voltage-to-current translation properties. This choice is nevertheless unusual, because current-steering digital- to-analog converters have a reputation for high performance with high power consumption. A time domain multiplexing scheme is presented such that a digital data set of any size is synchronously multiplexed through a finite array of converters, minimizing the total area and power consumption. I demonstrate the suitability of current-steering digital-to-analog converters for ultra low-power operation with a proof-of-concept design in a widely available 130 nm CMOS technology. In statistical simulation, the proposed digital-to-analog converter was capable of 8-bit, 100 kSps operation while consuming 231 nW of power from a 1 V supply

Modeling and analysis of power processing systems: Feasibility investigation and formulation of a methodology

A review is given of future power processing systems planned for the next 20 years, and the state-of-the-art of power processing design modeling and analysis techniques used to optimize power processing systems. A methodology of modeling and analysis of power processing equipment and systems has been formulated to fulfill future tradeoff studies and optimization requirements. Computer techniques were applied to simulate power processor performance and to optimize the design of power processing equipment. A program plan to systematically develop and apply the tools for power processing systems modeling and analysis is presented so that meaningful results can be obtained each year to aid the power processing system engineer and power processing equipment circuit designers in their conceptual and detail design and analysis tasks