Design Space Exploration in Cyber-Physical Systems

Cyber physical systems (CPS) integrate a variety of engineering areas such as control, mechanical and computer engineering in a holistic design effort. While interdependencies between the different disciplines are key attributes of CPS design science, little is known about the impact of design decisions of the cyber part on the overall system qualities. To investigate these interdependencies, this paper proposes a simulation-based Design Space Exploration (DSE) framework that considers detailed cyber system parameters such as cache size, bus width, and voltage levels in addition to physical and control parameters of the CPS. We propose an exploration algorithm that surfs the parameter configurations in the cyber physical sub-systems, in order to approximate the Pareto-optimal design points with regards to the trade-os among the design objectives, such as energy consumption and control stability. We apply the proposed framework to a network control system for an inverted-pendulum application. The presented holistic evaluation of the identified Pareto-points reveals the presence of non-trivial trade-os, which are imposed by the control, physical, and detailed cyber parameters. For instance the identified energy and control optimal design points comprise configurations with a wide range of CPU speeds, sample times and cache configuration following non-trivial zig-zag patterns. The proposed framework could identify and manage those trade-os and, as a result, is an imperative rst step to automate the search for superior CSP configurations

A Cross-Layer Approach for Minimizing Interference and Latency of Medium Access in Wireless Sensor Networks

In low power wireless sensor networks, MAC protocols usually employ periodic sleep/wake schedule to reduce idle listening time. Even though this mechanism is simple and efficient, it results in high end-to-end latency and low throughput. On the other hand, the previously proposed CSMA/CA-based MAC protocols have tried to reduce inter-node interference at the cost of increased latency and lower network capacity. In this paper we propose IAMAC, a CSMA/CA sleep/wake MAC protocol that minimizes inter-node interference, while also reduces per-hop delay through cross-layer interactions with the network layer. Furthermore, we show that IAMAC can be integrated into the SP architecture to perform its inter-layer interactions. Through simulation, we have extensively evaluated the performance of IAMAC in terms of different performance metrics. Simulation results confirm that IAMAC reduces energy consumption per node and leads to higher network lifetime compared to S-MAC and Adaptive S-MAC, while it also provides lower latency than S-MAC. Throughout our evaluations we have considered IAMAC in conjunction with two error recovery methods, i.e., ARQ and Seda. It is shown that using Seda as the error recovery mechanism of IAMAC results in higher throughput and lifetime compared to ARQ.Comment: 17 pages, 16 figure

Implementation and evaluation of the sensornet protocol for Contiki

Sensornet Protocol (SP) is a link abstraction layer between the network layer and the link layer for sensor networks. SP was proposed as the core of a future-oriented sensor node architecture that allows flexible and optimized combination between multiple coexisting protocols. This thesis implements the SP sensornet protocol on the Contiki operating system in order to: evaluate the effectiveness of the original SP services; explore further requirements and implementation trade-offs uncovered by the original proposal. We analyze the original SP design and the TinyOS implementation of SP to design the Contiki port. We implement the data sending and receiving part of SP using Contiki processes, and the neighbor management part as a group of global routines. The evaluation consists of a single-hop traffic throughput test and a multihop convergecast test. Both tests are conducted using both simulation and experimentation. We conclude from the evaluation results that SP's link-level abstraction effectively improves modularity in protocol construction without sacrificing performance, and our SP implementation on Contiki lays a good foundation for future protocol innovations in wireless sensor networks

Wireless Communication in Process Control Loop: Requirements Analysis, Industry Practices and Experimental Evaluation

Wireless communication is already used in process automation for process monitoring. The next stage of implementation of wireless technology in industrial applications is for process control. The need for wireless networked control systems has evolved because of the necessity for extensibility, mobility, modularity, fast deployment, and reduced installation and maintenance cost. These benefits are only applicable given that the wireless network of choice can meet the strict requirements of process control applications, such as latency. In this regard, this paper is an effort towards identifying current industry practices related to implementing process control over a wireless link and evaluates the suitability of ISA100.11a network for use in process control through experiments

Embedded Network Test-Bed for Validating Real-Time Control Algorithms to Ensure Optimal Time Domain Performance

The paper presents a Stateflow based network test-bed to validate real-time optimal control algorithms. Genetic Algorithm (GA) based time domain performance index minimization is attempted for tuning of PI controller to handle a balanced lag and delay type First Order Plus Time Delay (FOPTD) process over network. The tuning performance is validated on a real-time communication network with artificially simulated stochastic delay, packet loss and out-of order packets characterizing the network.Comment: 6 pages, 12 figure

An Adaptive Design Methodology for Reduction of Product Development Risk

Embedded systems interaction with environment inherently complicates understanding of requirements and their correct implementation. However, product uncertainty is highest during early stages of development. Design verification is an essential step in the development of any system, especially for Embedded System. This paper introduces a novel adaptive design methodology, which incorporates step-wise prototyping and verification. With each adaptive step product-realization level is enhanced while decreasing the level of product uncertainty, thereby reducing the overall costs. The back-bone of this frame-work is the development of Domain Specific Operational (DOP) Model and the associated Verification Instrumentation for Test and Evaluation, developed based on the DOP model. Together they generate functionally valid test-sequence for carrying out prototype evaluation. With the help of a case study 'Multimode Detection Subsystem' the application of this method is sketched. The design methodologies can be compared by defining and computing a generic performance criterion like Average design-cycle Risk. For the case study, by computing Average design-cycle Risk, it is shown that the adaptive method reduces the product development risk for a small increase in the total design cycle time.Comment: 21 pages, 9 figure