High frequency inverter-transformer-cycloconverter system for DC to AC (3-phase) power conversion

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.This thesis is concerned with a 3-phase multistage high frequency link DC to AC power conversion with a novel inverter-cycloconverter circuitry. The conversion system is composed of a high frequency PWM inverter, step-up high frequency transformer and cycloconverter with bidirectional switching devices. In first stage the DC voltage of the power source , say a submarine battery, is inverted to a system of 3-phase sinusoidally modulated I kHz alternative wave forms. For this purpose a suggested optimized PWM technique for 3-phase inverter operation is adopted, in which harmonic components up to 17 th ( 17 kHz) are eliminated from the inverter output voltages. In the second stage, for DC input isolation from AC output and also for a voltage transformation ( here stepping-up )a high frequency ( size reduced ) transformer is employed. Generalized high frequency operation, influence and side effects of the transformer on overall system design & performance is investigated. In the final stage the 1 kHz -to- 50 Hz conversion process is accomplished by a 3-phase cycloconverter. The proposed "nonlinear modulation strategy" for cycloconverter output voltage and associated harmonic analysis is demonstrated, in which the harmonic components up to 38th (1.9 kHz ) are eliminated from the conversion system output voltage. To assess the suggested functioning principles for the inverter & cycloconverter , the prototype conversion system was developed. Some design criteria and switching device selection are presented, together with different voltage & current wave forms of the prototype system under resistive & inductive load (induction motor) and their respective spectra

Ac-voltage harmonic control for stand-alone and weak-grid-tied converter

This article presents an ac voltage controller that can operate under a wide range of loads, thanks to its high robustness to plant-model variations. A robust voltage controller is required in a droop-controlled inverter that operates connected to a grid or in island mode with other generators. In such modes of operation, the voltage source converter can experience large load-impedance variations depending on the number of parallel generators or the grid impedance value. Concerning the controller performance, the transient response is improved by selectively minimizing the output impedance of the system at the frequencies that typically contain the largest components of the output current. Complete harmonic control is achieved due to its zero output impedance at a set of design-selected frequencies. The proposed controller only measures the output voltage, and it contains a single-loop structure that uses all available bandwidth. In addition, a fast converter-current estimator provides protection against faults and inrush output currents. The design process only requires, as input parameters, the LC filter values, the sampling frequency, and a set of harmonics where load-current circulation is expected.European Commission | Ref. DPI2016-75832Ministerio de Educación, Cultura y Deporte | Ref. FPU14/0068

Generalised multistage modelling and tuning algorithm for class EF and class Φ inverters to eliminate iterative retuning

The additional complexity of Class EF and Class Φ inverters compared to their Class E counterparts, combined with parasitic effects becoming more prevalent as frequency and power levels increase, results in poor accuracy from traditional design methods, and usually additional iterations of manual retuning are required. In this work we propose an approach to simulating and tuning Class EF/Φ inverters, with various levels of accuracy depending on the level of knowledge of the system parasitics. Our method is comprised of a combination of analytic and numerical solving methods thus providing both insight on the progression of the algorithm and computational robustness. The aim of our algorithm formulation is to enable solutions to be found in an automated and fast way. The novelty in our work lies in the design method's concurrent capability to provide a generalised set of design inputs (e.g. DC to AC current gain, arbitrary drain voltage slope at turn on, Φ- branch resonance, etc.), inclusion of board and device non-linear parasitics, and the ability to design within the set of preferred component values. An example is shown for the design of a 50 W, 13.56 MHz inverter where the experimental setup approaches the theoretical efficiency of 97%. The algorithm changes the values of the components over 5% to 50% and improves the simulated waveform accuracy by 2 to 12 times compared to the design method based on first order approximations

Synthesis and Optimization of Reversible Circuits - A Survey

Reversible logic circuits have been historically motivated by theoretical research in low-power electronics as well as practical improvement of bit-manipulation transforms in cryptography and computer graphics. Recently, reversible circuits have attracted interest as components of quantum algorithms, as well as in photonic and nano-computing technologies where some switching devices offer no signal gain. Research in generating reversible logic distinguishes between circuit synthesis, post-synthesis optimization, and technology mapping. In this survey, we review algorithmic paradigms --- search-based, cycle-based, transformation-based, and BDD-based --- as well as specific algorithms for reversible synthesis, both exact and heuristic. We conclude the survey by outlining key open challenges in synthesis of reversible and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table

Asynchronous Networks and Event Driven Dynamics

Real-world networks in technology, engineering and biology often exhibit dynamics that cannot be adequately reproduced using network models given by smooth dynamical systems and a fixed network topology. Asynchronous networks give a theoretical and conceptual framework for the study of network dynamics where nodes can evolve independently of one another, be constrained, stop, and later restart, and where the interaction between different components of the network may depend on time, state, and stochastic effects. This framework is sufficiently general to encompass a wide range of applications ranging from engineering to neuroscience. Typically, dynamics is piecewise smooth and there are relationships with Filippov systems. In the first part of the paper, we give examples of asynchronous networks, and describe the basic formalism and structure. In the second part, we make the notion of a functional asynchronous network rigorous, discuss the phenomenon of dynamical locks, and present a foundational result on the spatiotemporal factorization of the dynamics for a large class of functional asynchronous networks

Distributed Models for Filter Synthesis

The limitations of filter synthesis methods based on classic equivalent circuits with the enhanced distributed models and synthesis procedures able to overcome such limitations are presented. A modified procedure that corrects the waveguide lengths has been proposed. The input and output reflection coefficients of the ideal prototype steps are real. The shunt capacitive effect introduces a phase shift in the reflection coefficients of each waveguide step. The representation of the filter structure can be improved if the waveguide steps are analyzed with a full-wave electromagnetic (EM) simulator, and their responses are stored in the form of ABCD matrices. The desired filter passband cutoff frequency was 11 GHz, with a specified return loss of 25 dB, and a gap height greater than 4.25 mm. High-power applications with wide stopbands often require impractical waveguide sections. The accurate EM simulators are used to find an almost exact equivalence between the prototype and the filter parts.Boria Esbert, VE.; Soto Pacheco, P.; Cogollos Borras, S. (2011). Distributed Models for Filter Synthesis. IEEE Microwave Magazine. 12(6):87-100. doi:10.1109/MMM.2011.942010S8710012

A novel faulted section location technique for future active distribution networks

Distribution Network Operators (DNOs) face increasingly higher challenges to preserve quality and continuity of supply due to the widespread penetration of Distributed Energy Resources (DER) [1–8]. In parallel, more advanced technologies are being introduced into secondary substations for better observability and controllability. These features provided via instrumented substation assets and Information Communication Technologies (ICT) present opportunities for the development and implementation of new functions aiming to the effective operation and monitoring of active distribution networks [9–14]. This thesis focuses on one of these functionalities – that is, leveraging the ability of Low Voltage (LV) sensors to locate 11 kV unsymmetrical faults by monitoring and processing the network voltage profile during fault conditions. In particular, a novel technique has been developed which identifies the Faulted Section (FS) of the Medium Voltage (MV) feeder after a fault has occurred. The proposed algorithm, of which the successful operation depends solely on distributed LV voltage monitoring devices, represents the main contribution of the research work. A key characteristic is that, although the LV sensors connected at the secondary side of MV/LV step-down transformers require communication to transmit the data to a central point, they do not require time synchronisation. The technique facilitates the fault location procedure, which is of major importance as it accelerates restoration, reduces the system downtime, minimises repair cost, and hence, increases the overall availability and reliability of the distribution network. Moreover, the thesis deals with the challenges related to the complexity of modern distribution networks, taking into account ring topologies, MV lateral connections, pre-fault load unbalance and the presence of DERs. In this sense, the empirical characterisation of grid connection stability and fault response of small scale commercially available LV PV inverters was realised. The purpose was twofold: 1) highlight the diversity among the inverters’ responses as observed during the testing and indicate the risk of loss of PV generation during typical MV and HV level faults and 2) develop a dynamic model representing the behaviour of a real inverter under the applied physical testing conditions. The particular model was deployed in the power system studies conducted, aiding the evaluation of the FS location technique. Laboratory investigation was also carried out at the facilities of the Power Networks Demonstration Centre (PNDC) to further examine the performance of the developed faulted section location algorithm. The tests were performed in both MV radial and ring PNDC network configurations and measurements were acquired from various LV test-bays. It was demonstrated that the scheme can reliably identify the faulted section of the line while consistently maintaining high accuracy across a wide range of fault scenarios. Further sensitivity analysis demonstrates that the proposed scheme is robust against partial loss of communications and noise interference. The thesis concludes with an overview of future work that is required to further advance the concepts demonstrated.Distribution Network Operators (DNOs) face increasingly higher challenges to preserve quality and continuity of supply due to the widespread penetration of Distributed Energy Resources (DER) [1–8]. In parallel, more advanced technologies are being introduced into secondary substations for better observability and controllability. These features provided via instrumented substation assets and Information Communication Technologies (ICT) present opportunities for the development and implementation of new functions aiming to the effective operation and monitoring of active distribution networks [9–14]. This thesis focuses on one of these functionalities – that is, leveraging the ability of Low Voltage (LV) sensors to locate 11 kV unsymmetrical faults by monitoring and processing the network voltage profile during fault conditions. In particular, a novel technique has been developed which identifies the Faulted Section (FS) of the Medium Voltage (MV) feeder after a fault has occurred. The proposed algorithm, of which the successful operation depends solely on distributed LV voltage monitoring devices, represents the main contribution of the research work. A key characteristic is that, although the LV sensors connected at the secondary side of MV/LV step-down transformers require communication to transmit the data to a central point, they do not require time synchronisation. The technique facilitates the fault location procedure, which is of major importance as it accelerates restoration, reduces the system downtime, minimises repair cost, and hence, increases the overall availability and reliability of the distribution network. Moreover, the thesis deals with the challenges related to the complexity of modern distribution networks, taking into account ring topologies, MV lateral connections, pre-fault load unbalance and the presence of DERs. In this sense, the empirical characterisation of grid connection stability and fault response of small scale commercially available LV PV inverters was realised. The purpose was twofold: 1) highlight the diversity among the inverters’ responses as observed during the testing and indicate the risk of loss of PV generation during typical MV and HV level faults and 2) develop a dynamic model representing the behaviour of a real inverter under the applied physical testing conditions. The particular model was deployed in the power system studies conducted, aiding the evaluation of the FS location technique. Laboratory investigation was also carried out at the facilities of the Power Networks Demonstration Centre (PNDC) to further examine the performance of the developed faulted section location algorithm. The tests were performed in both MV radial and ring PNDC network configurations and measurements were acquired from various LV test-bays. It was demonstrated that the scheme can reliably identify the faulted section of the line while consistently maintaining high accuracy across a wide range of fault scenarios. Further sensitivity analysis demonstrates that the proposed scheme is robust against partial loss of communications and noise interference. The thesis concludes with an overview of future work that is required to further advance the concepts demonstrated

Unfaithful Glitch Propagation in Existing Binary Circuit Models

We show that no existing continuous-time, binary value-domain model for digital circuits is able to correctly capture glitch propagation. Prominent examples of such models are based on pure delay channels (P), inertial delay channels (I), or the elaborate PID channels proposed by Bellido-D\'iaz et al. We accomplish our goal by considering the solvability/non-solvability border of a simple problem called Short-Pulse Filtration (SPF), which is closely related to arbitration and synchronization. On one hand, we prove that SPF is solvable in bounded time in any such model that provides channels with non-constant delay, like I and PID. This is in opposition to the impossibility of solving bounded SPF in real (physical) circuit models. On the other hand, for binary circuit models with constant-delay channels, we prove that SPF cannot be solved even in unbounded time; again in opposition to physical circuit models. Consequently, indeed none of the binary value-domain models proposed so far (and that we are aware of) faithfully captures glitch propagation of real circuits. We finally show that these modeling mismatches do not hold for the weaker eventual SPF problem.Comment: 23 pages, 15 figure