Assessing the effectiveness of different test approaches for power devices in a PCB

Power electronic systems employing Printed Circuit Boards (PCBs) are broadly used in many applications, including some safety-critical ones. Several standards (e.g., ISO26262 for the automotive sector and DO-178 for avionics) mandate the adoption of effective test procedures for all electronic systems. However, the metrics to be used to compute the effectiveness of the adopted test procedures are not so clearly defined for power devices and systems. In the last years, some commercial fault simulation tools (e.g., DefectSim by Mentor Graphics and TestMAX by Synopsys) for analog circuits have been introduced, together with some new fault models. With these new tools, systematic analog fault simulation finally became practically feasible. The aim of this paper is twofold: first, we propose a method to extend the usage of the new analog fault models to power devices, thus allowing to compute a Fault Coverage figure for a given test. Secondly, we adopt the method on a case study, for which we quantitatively evaluate the effectiveness of some test procedures commonly used at the PCB level for the detection of faults inside power devices. A typical Power Supply Unit (PSU) used in industrial products, including power transistors and power diodes, is considered. The analysis of the gathered results shows that using the new method we can identify the main points of strength / weakness of the different test solutions in a quantitative and deterministic manner, and pinpoint the faults escaping to each one

A test method for analog circuits : using sensitivity analysis and the singular value decomposition

XVII+C.3hlm.;24c

Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

Since the last century, the exponential growth of the semiconductor industry has led to the creation of tiny and complex integrated circuits, e.g., sensors, actuators, and smart power. Innovative techniques are needed to ensure the correct functionality of analog devices that are ubiquitous in every smart system. The ISO 26262 standard for functional safety in the automotive context specifies that fault injection is necessary to validate all electronic devices. For decades, standardization of defect modeling and injection mainly focused on digital circuits and, in a minor part, on analog ones. An initial attempt is being made with the IEEE P2427 draft standard that started to give a structured and formal organization to the analog testing field. Various methods have been proposed in the literature to speed up the fault simulation of the defect universe for an analog circuit. A more limited number of papers seek to reduce the overall simulation time by reducing the number of defects to be simulated. This literature survey describes the state-of-the-art of analog defect injection and fault simulation methods. The survey is based on the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) methodological flow, allowing for a systematic and complete literature survey. Each selected paper has been categorized and presented to provide an overview of all the available approaches. In addition, the limitations of the various approaches are discussed by showing possible future directions

Communication Subsystems for Emerging Wireless Technologies

The paper describes a multi-disciplinary design of modern communication systems. The design starts with the analysis of a system in order to define requirements on its individual components. The design exploits proper models of communication channels to adapt the systems to expected transmission conditions. Input filtering of signals both in the frequency domain and in the spatial domain is ensured by a properly designed antenna. Further signal processing (amplification and further filtering) is done by electronics circuits. Finally, signal processing techniques are applied to yield information about current properties of frequency spectrum and to distribute the transmission over free subcarrier channels

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations

Modeling and Generation of Test Patterns for Mixed-Signal Boards: Dealing With Basic Signals

International audienceIn the context of maintenance testing and diagnosis of faulty boards, a functional FSM (Finite State Machine)-based model for mixed-signal board has been introduced. The board is broken down into interconnected functional blocks. Each block has an associated functional model which describes its behavior and a test model which specifies how the block can be efficiently tested. A test model for a block is created by merging its functional model and a chosen test strategy. The board checking consists in testing each block individually using its test model and functional models of other blocks. Test patterns for a component are generated by covering the transitions of its test model and propagation to primary inputs/outputs through functional models of other blocks. The board test data set is built by using the test patterns for all the blocks of the board. The current improvement of the method deals with basic signals

Cost modelling and concurrent engineering for testable design

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.As integrated circuits and printed circuit boards increase in complexity, testing becomes a major cost factor of the design and production of the complex devices. Testability has to be considered during the design of complex electronic systems, and automatic test systems have to be used in order to facilitate the test. This fact is now widely accepted in industry. Both design for testability and the usage of automatic test systems aim at reducing the cost of production testing or, sometimes, making it possible at all. Many design for testability methods and test systems are available which can be configured into a production test strategy, in order to achieve high quality of the final product. The designer has to select from the various options for creating a test strategy, by maximising the quality and minimising the total cost for the electronic system. This thesis presents a methodology for test strategy generation which is based on consideration of the economics during the life cycle of the electronic system. This methodology is a concurrent engineering approach which takes into account all effects of a test strategy on the electronic system during its life cycle by evaluating its related cost. This objective methodology is used in an original test strategy planning advisory system, which allows for test strategy planning for VLSI circuits as well as for digital electronic systems. The cost models which are used for evaluating the economics of test strategies are described in detail and the test strategy planning system is presented. A methodology for making decisions which are based on estimated costing data is presented. Results of using the cost models and the test strategy planning system for evaluating the economics of test strategies for selected industrial designs are presented

Space station automation of common module power management and distribution

The purpose is to automate a breadboard level Power Management and Distribution (PMAD) system which possesses many functional characteristics of a specified Space Station power system. The automation system was built upon 20 kHz ac source with redundancy of the power buses. There are two power distribution control units which furnish power to six load centers which in turn enable load circuits based upon a system generated schedule. The progress in building this specified autonomous system is described. Automation of Space Station Module PMAD was accomplished by segmenting the complete task in the following four independent tasks: (1) develop a detailed approach for PMAD automation; (2) define the software and hardware elements of automation; (3) develop the automation system for the PMAD breadboard; and (4) select an appropriate host processing environment

Modelling methods for testability analysis of analog integrated circuits based on pole-zero analysis

Testability analysis for analog circuits provides valuable information for designers and test engineers. Such information includes a number of testable and nontestable elements of a circuit, ambiguity groups, and nodes to be tested. This information is useful for solving the fault diagnosis problem. In order to verify the functionality of analog circuits, a large number of specifications have to be checked. However, checking all circuit specifications can result in prohibitive testing times on expensive automated test equipment. Therefore, the test engineer has to select a finite subset of specifications to be measured. This subset of specifications must result in reducing the test time and guaranteeing that no faulty chips are shipped. This research develops a novel methodology for testability analysis of linear analog circuits based on pole-zero analysis and on pole-zero sensitivity analysis. Based on this methodology, a new interpretation of ambiguity groups is provided relying on the circuit theory. The testability analysis methodology can be employed as a guideline for constructing fault diagnosis equations and for selecting the test nodes. We have also proposed an algorithm for selecting specifications that need to be measured. The element testability concept will be introduced. This concept provides the degree of difficulty in testing circuit elements. The value of the element testability can easily be obtained using the pole sensitivities. Then, specifications which need to be measured can be selected based on this concept. Consequently, the selected measurements can be utilized for reducing the test time without sacrificing the fault coverage and maximizing the information for fault diagnosis