Innovative Wireless Power Receiver for Inductive Coupling and Magnetic Resonance Applications

This chapter presents a wireless power receiver for inductive coupling and magnetic resonance applications. The active rectifier with shared delay-locked loop (DLL) is proposed to achieve the high efficiency for different operation frequencies. In the DC–DC converter, the phase-locked loop is adopted for the constant switching frequency in the process, voltage, and temperature variation to solve the efficiency reduction problem, which results in the heat problem. An automatic mode switching between pulse width modulation and pulse frequency modulation is also adopted for the high efficiency over the wide output power. This chip is implemented using 0.18 μm BCD technology with an active area of 5.0 mm × 3.5 mm. The maximum efficiency of the active rectifier is 92%, and the maximum efficiency of the DC–DC converter is 92% when the load current is 700 mA

메모리 인터페이스를 위한 4 레벨 펄스 진폭 변조 쿼터 레이트 수신기 설계

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 김수환.본 연구에서는 메모리 인터페이스를 위한 4 레벨 펄스 진폭 변조 (PAM-4) 수신기와 직교 클록을 생성하는 직교 신호 보정기를 제안된다. 데이터 센터에서 증가하는 IP 트래픽은 고속 및 저전력 메모리 인터페이스에 대한 수요를 증가시켜왔다. 이러한 요구를 만족시키기 위해 클럭 및 나이퀴스트 주파수를 높이지 않고도 데이터 전송률을 높일 수 있는 PAM-4 신호가 주목을 받고 있다. PAM-4 신호는 제로 비 복귀 신호 (NRZ) 보다 3배 낮은 수직 마진을 가지며, 이는 결정 피드백 이퀄라이저 내 슬라이스의 클럭-큐 딜레이를 증가시키며, 이로 인해 PAM-4 결정 피드백 이퀄라이저의 성능을 제한하는 요인이다. 본 연구에서는 인버터 기반의 합산기를 이용, 선택적으로 신호를 증폭시키는 결정 피드백 이퀄라이저를 사용함으로써 슬라이서의 전력 소모를 증가시키지 않으면서 슬라이서의 클럭-큐 딜레이를 줄일 수 있다. 또한, 적응형 지연 이득 컨트롤러를 포함하는 직교 신호 보정기는 높은 정확도와 빠른 스큐 보정으로 쿼드러처 클럭 간의 스큐를 교정할 수 있다. 선택적 눈 증폭 결정 피드백 이퀄라이저와 적응형 지연 이득 컨트롤러를 포함하는 직교 신호 보정기의 성능을 검증하기 위해 프로토타입 칩을 제작하였다. 제작된 칩은 65 nm CMOS 공정으로 제작되었다. 프로토타입 칩은 24 Gb/s/pin 에서 10-12 의 비트 에러율을 100 mUI 의 신호 너비로 달성하였다. 프로토타입 칩 내 PAM-4 수신기는 0.73 pJ/b 의 에너지 효율을 갖는다. 또한 적응형 지연 이득 컨트롤러를 포함하는 직교 신호 보정기는 3 GHz 쿼드러처 클럭 간 최대 21.2 ps 의 스큐를 0.8 ps 까지 줄일 수 있으며, 이 때 76.9 ns 의 교정 시간을 갖는다. 제안하는 직교 신호 보정기는 3 GHz 에서 2.15 mW/GHz 의 전력 효율을 갖는다.A four-level pulse amplitude modulation (PAM-4) receiver, and a quadrature signal corrector (QSC) that generates quadrature clocks for memory interfaces is presented. Increasing IP traffic in data centers has increased the demand for high-speed and low-power memory interfaces. To satisfy this demand, PAM-4 signaling, which can increase data-rate without increasing clock and Nyquist frequency, is received considerable attention. PAM- signaling has vertical which three times lower than non-return-to-zero (NRZ) signaling, which makes the clock-to-Q delay of the slicer in the decision feedback equalizer (DFE) increases. This makes the DFE difficult to satisfy the timing constraint. In this paper, by using a DFE with inverter-based summers, the clock-to-Q delay of the slicer can be reduced without increasing the power consumption of the slicers. Also, the QSC using an adaptive delay gain controller can correct the skew between the quadrature clock with low skew and short correction time. The prototype receiver including the DFE with the inverter-based summer and the QSC using the adaptive delay gain controller was fabricated in 65 nm CMOS process. The prototype chip can achieve a bit error rate (BER) of 10-12 at 24 Gb/s/pin, and at this time, an eye width of 100 mUI is secured. The efficiency of the receiver is 0.73 pJ/b. In addition, the QSC cna reduce the maximum 21.2 ps of skew between 3 GHz quadrature clocks to 0.8 ps and has a correction time of 76.9 ns. The efficiency of the QSC is 2.15 mW/GHz.ABSTRACT 1 CONTENTS 3 LIST OF FIGURES 5 LIST OF TABLE 9 CHAPTER 1 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 PAM-4 SIGNALING 7 1.2.1 DESIGN CONSIDERATIONS ON PAM-4 RECEIVER 10 1.2.2 PRIOR WORKS 14 1.3 QUARTER-RATE ARCHITECTURE 18 1.3.1 DESIGN CONSIDERATION ON QUARTER-RATE ARCHITECTURE 20 1.3.2 PRIOR WORKS 25 1.4 SUMMARY 28 1.5 THESIS ORGANIZATION 30 CHAPTER 2 31 CONCEPTS OF DFE WITH INVERTER-BASED SUMMER 31 2.1 CONCEPTUAL ARCHITECTURE OF DFE WITH INVERTER-BASED SUMMER 32 2.2 DESIGN CONSIDERATION OF INVERTER-BASED SUMMER 37 CHAPTER 3 41 CONCEPTS OF QUADRATURE SIGNAL CORRECTOR USING ADAPTIVE DELAY GAIN CONTROLLER 41 3.1 OPERATION OF PROPOSED QUADRATURE SIGNAL CORRECTOR 42 3.2 LOOP FILTER INCLUDING ADAPTIVE DELAY GAIN CONTROLLER 45 CHAPTER 4 48 ARCHITECTURE AND IMPLEMENTATION 48 4.1 OVERALL ARCHITECTURE 49 4.2 ANALOG FRONT END 52 4.3 DECISION FEEDBACK EQUALIZER WITH INVERTER-BASED SUMMER 54 4.4 CLOCK PATH 62 4.5 QUADRATURE SIGNAL CORRECTOR WITH ADAPTIVE DELAY GAIN CONTROLLER 63 CHAPTER 5 70 EXPERIMENTAL RESULTS 70 5.1 EXPERIMENTAL SETUP 70 5.2 EXPERIMENTAL RESULTS 74 5.2.1 MEASUREMENT RESULTS OF PAM-4 RECEIVER WITH DECISION FEEDBACK EQUALIZER USING INVERTER-BASED SUMMER 74 5.2.2 MEASUREMENT RESULTS OF QUADRATURE SIGNAL CORRECTOR USING ADAPTIVE DELAY GAIN CONTROLLER 77 CHAPTER 6 83 CONCLUSION 83 BIBLIOGRAPHY 86박

Ultra Low Power Analog Circuits for Wireless Sensor Node System.

This thesis will discuss essential analog circuit blocks required in ultra-low power wireless sensor node systems. A wireless sensor network system requires very high energy and power efficiency which is difficult to achieve with traditional analog circuits. First, 5.58nW real time clock using a DLL (Delay Locked Loop)-assisted pulse-driven crystal oscillator is discussed. In this circuit, the operational amplifier used in the traditional circuit was replaced with pulsed drivers. The pulse was generated at precise timing by a DLL. The circuit parts operate in different supply levels, generated on chip by using a switched capacitor network. The circuit was tested at different supply voltage and temperature. Its frequency characteristic along with power consumption were measured and compared to the traditional circuit. Next, a Schmitt trigger based pulse-driven crystal oscillator is discussed. In the first chapter, a DLL was used to generate a pulse with precise timing. However, testing results and recent study showed that the crystal oscillator can sustain oscillation even with inaccurate pulse timing. In this chapter, pulse location is determined by the Schmitt trigger. Simulation results show that this structure can still sustain oscillation at different process corners and temperature. In the next chapter, a sub-nW 8 bit SAR ADC (Successive Approximation Analog-to-Digital Converter) using transistor-stack DAC (Digital-to-Analog Converter) is discussed. To facilitate design effort and reduce the layout dependent effect, a conventional capacitive DAC was replaced with transistor-stack DAC with a 255:1 multiplexer. The control logic was designed with both TSPC (True Single Phase Clock) and CMOS logic to minimize transistor count. The ADC was implemented in a 65nm CMOS process and tested at different sampling rates and input signal frequency. Its linearity and power consumption was measured. Also, a similar design was implemented and tested using 180nm CMOS process as part of a sensor node system. Lastly, a multiple output level voltage regulator using a switched capacitor network for low-cost system is discussed.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/111626/1/dmyoon_1.pd

Wireless Power Transfer

Wireless power transfer techniques have been gaining researchers' and industry attention due to the increasing number of battery-powered devices, such as mobile computers, mobile phones, smart devices, intelligent sensors, mainly as a way to replace the standard cable charging, but also for powering battery-less equipment. The storage capacity of batteries is an extremely important element of how a device can be used. If we talk about battery-powered electronic equipment, the autonomy is one factor that may be essential in choosing a device or another, making the solution of remote powering very attractive. A distinction has to be made between the two forms of wireless power transmission, as seen in terms of how the transmitted energy is used at the receiving point: - Transmission of information or data, when it is essential for an amount of energy to reach the receiver to restore the transmitted information; - Transmission of electric energy in the form of electromagnetic field, when the energy transfer efficiency is essential, the power being used to energize the receiving equipment. The second form of energy transfer is the subject of this book

Flexible Computing Architecture for Real Time Skin Detection

In both the Air Force and Search and Rescue Communities, there is a current need to detect and characterize persons. Existing methods use red-green-blue (RGB) imagery, but produce high false alarm rates. New technology in multi-spectral skin detection is better than the existing RGB methods, but lacks a control and processing architecture to make them efficient for real time problems. We hypothesize that taking a minimalistic approach to the software design, we can perform image preprocessing, feature computation, and skin detection in real time. A number of applications require accurate detection and characterization of persons, human measurement and signature intelligence (H-MASINT), and SAR in particular. H-MASINT requires it for the detection of persons in images so other processing can be performed. It is useful in the SAR community as a method of finding persons partly obscured, in remote regions, and either living or deceased. We have developed a modular computing architecture to perform the acquisition and processing in real time, as well as separate programs to perform processing and analysis of images post-acquisition. The architecture is flexible, as one can easily add additional functionality to meet growing demands. All programs were organized using a basic Model-View-Controller design, designed using Universal Modeling Language principles, and coded using a bottom-up approach. Based on the results presented in this thesis, image acquisition, processing, skin detection, viewing, and saving can be performed in real time, at nearly 10 fps. Not only does this support the SAR community, the Air Force now has a new capability to help address its H-MASINT mission

Beamforming ultra-wideband transmitter

Master'sMASTER OF ENGINEERIN

Radiation Hardened by Design Methodologies for Soft-Error Mitigated Digital Architectures

abstract: Digital architectures for data encryption, processing, clock synthesis, data transfer, etc. are susceptible to radiation induced soft errors due to charge collection in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs). Radiation hardening by design (RHBD) techniques such as double modular redundancy (DMR) and triple modular redundancy (TMR) are used for error detection and correction respectively in such architectures. Multiple node charge collection (MNCC) causes domain crossing errors (DCE) which can render the redundancy ineffectual. This dissertation describes techniques to ensure DCE mitigation with statistical confidence for various designs. Both sequential and combinatorial logic are separated using these custom and computer aided design (CAD) methodologies. Radiation vulnerability and design overhead are studied on VLSI sub-systems including an advanced encryption standard (AES) which is DCE mitigated using module level coarse separation on a 90-nm process with 99.999% DCE mitigation. A radiation hardened microprocessor (HERMES2) is implemented in both 90-nm and 55-nm technologies with an interleaved separation methodology with 99.99% DCE mitigation while achieving 4.9% increased cell density, 28.5 % reduced routing and 5.6% reduced power dissipation over the module fences implementation. A DMR register-file (RF) is implemented in 55 nm process and used in the HERMES2 microprocessor. The RF array custom design and the decoders APR designed are explored with a focus on design cycle time. Quality of results (QOR) is studied from power, performance, area and reliability (PPAR) perspective to ascertain the improvement over other design techniques. A radiation hardened all-digital multiplying pulsed digital delay line (DDL) is designed for double data rate (DDR2/3) applications for data eye centering during high speed off-chip data transfer. The effect of noise, radiation particle strikes and statistical variation on the designed DDL are studied in detail. The design achieves the best in class 22.4 ps peak-to-peak jitter, 100-850 MHz range at 14 pJ/cycle energy consumption. Vulnerability of the non-hardened design is characterized and portions of the redundant DDL are separated in custom and auto-place and route (APR). Thus, a range of designs for mission critical applications are implemented using methodologies proposed in this work and their potential PPAR benefits explored in detail.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

The Design of Low Power Ultra-Wideband Transceiver

Ph.DDOCTOR OF PHILOSOPH

Autonomisen multikopteriparven hallinta etsintä- ja pelastustehtävissä

This thesis presents the requirements and implementation of a Ground Control Station (GCS) application for controlling a fleet of multicopters to perform a Search And Rescue (SAR) mission. The requirements are put together by analysing existing drone types, SAR practices, and available GCS applications. Multicopters are found to be the most feasible drone to use for the SAR use case because of their maneuverability, despite not having the best endurance. Several existing area coverage methods are presented and their usefulness is analyzed for SAR scenarios where different amounts of prior knowledge is available. It is stated that most search patterns can be used with a fleet of drones, by creating drone formations and by dividing the target area into sub-areas. It is noted that most currently available GCS applications are focused on controlling a single drone for either industrial or hobby use. A proof of concept prototype is developed on top of an open source GCS and tested in field tests. Based on all the previous learnings from the protype and research, a new GCS is designed and developed. The development on optimizing communications between the GCS and the autopilot leads to a filed patent application. The new software is tested with three multicopters in a water rescue scenario and several user interface improvements are made as a result of the learnings. The development of a GCS for controlling a drone fleet for search and rescue is proven feasible.Työssä esitetään multikopteriparven hallintaan käytettävän Ground Control Station (GCS) ohjelmiston vaatimukset ja toteutus Search And Rescue (SAR) etsintä- ja pelastustehtävien suorittamiseksi. Vaatimukset kootaan yhteen analysoimalla saatavilla olevia droonityyppejä, SAR pelastuskäytäntöjä, sekä GCS ohjelmistoja. Multikopterit osoittautuvat liikkuvuutensa ansiosta pelastustehtäviin sopivimmaksi vaihtoehdoksi, vaikka niiden saavutettavissa oleva lentoaika ei ole parhaimmasta päästä. Erilaisia etsintämetodeja esitetään alueiden kattamiseksi ja niiden hyödyllisyyttä analysoidaan SAR tilanteissa, joissa ennakkotietoa on saatavilla vaihtelevasti. Osoitetaan, että useimpia etsintäalgoritmeja voidaan hyödyntää drooniparvella, muodostamalla lentomuodostelmia, sekä jakamalla kohdealue pienempiin osa-alueisiin. Huomataan, että suurin osa tällä hetkellä saatavilla olevista GCS ohjelmistoista on suunnattu teollisuuden tai harrastelijoiden käyttöön, pääasiassa yksittäisen droonin hallintaan. Prototyyppi kehitetään avoimen lähdekoodin GCS ohjelmiston pohjalta ja testataan kenttätesteissä. Tästä saadun tiedon avulla suunnitellaan ja kehitetään uusi GCS ohjelmisto. Kehitystyö viestinnän optimoinniksi autopilotin ja GCS ohjelmiston välillä johtaa patenttihakemukseen. Uusi ohjelmisto testataan kolmella multikopterilla vesipelastustilanteessa ja sen seurauksena käyttöliittymään tehdään useita parannuksia. GCS ohjelmiston luominen drooniparven hallintaan etsintä- ja pelastustehtävissä todetaan mahdolliseksi

Integrated Electronics for Wireless Imaging Microsystems with CMUT Arrays

Integration of transducer arrays with interface electronics in the form of single-chip CMUT-on-CMOS has emerged into the field of medical ultrasound imaging and is transforming this field. It has already been used in several commercial products such as handheld full-body imagers and it is being implemented by commercial and academic groups for Intravascular Ultrasound and Intracardiac Echocardiography. However, large attenuation of ultrasonic waves transmitted through the skull has prevented ultrasound imaging of the brain. This research is a prime step toward implantable wireless microsystems that use ultrasound to image the brain by bypassing the skull. These microsystems offer autonomous scanning (beam steering and focusing) of the brain and transferring data out of the brain for further processing and image reconstruction. The objective of the presented research is to develop building blocks of an integrated electronics architecture for CMUT based wireless ultrasound imaging systems while providing a fundamental study on interfacing CMUT arrays with their associated integrated electronics in terms of electrical power transfer and acoustic reflection which would potentially lead to more efficient and high-performance systems. A fully wireless architecture for ultrasound imaging is demonstrated for the first time. An on-chip programmable transmit (TX) beamformer enables phased array focusing and steering of ultrasound waves in the transmit mode while its on-chip bandpass noise shaping digitizer followed by an ultra-wideband (UWB) uplink transmitter minimizes the effect of path loss on the transmitted image data out of the brain. A single-chip application-specific integrated circuit (ASIC) is de- signed to realize the wireless architecture and interface with array elements, each of which includes a transceiver (TRX) front-end with a high-voltage (HV) pulser, a high-voltage T/R switch, and a low-noise amplifier (LNA). Novel design techniques are implemented in the system to enhance the performance of its building blocks. Apart from imaging capability, the implantable wireless microsystems can include a pressure sensing readout to measure intracranial pressure. To do so, a power-efficient readout for pressure sensing is presented. It uses pseudo-pseudo differential readout topology to cut down the static power consumption of the sensor for further power savings in wireless microsystems. In addition, the effect of matching and electrical termination on CMUT array elements is explored leading to new interface structures to improve bandwidth and sensitivity of CMUT arrays in different operation regions. Comprehensive analysis, modeling, and simulation methodologies are presented for further investigation.Ph.D