Effective electrothermal analysis of electronic devices and systems with parameterized macromodeling

We propose a parameterized macromodeling methodology to effectively and accurately carry out dynamic electrothermal (ET) simulations of electronic components and systems, while taking into account the influence of key design parameters on the system behavior. In order to improve the accuracy and to reduce the number of computationally expensive thermal simulations needed for the macromodel generation, a decomposition of the frequency-domain data samples of the thermal impedance matrix is proposed. The approach is applied to study the impact of layout variations on the dynamic ET behavior of a state-of-the-art 8-finger AlGaN/GaN high-electron mobility transistor grown on a SiC substrate. The simulation results confirm the high accuracy and computational gain obtained using parameterized macromodels instead of a standard method based on iterative complete numerical analysis

Variable domain transformation for linear PAC analysis of mixed-signal systems

This paper describes a method to perform linear AC analysis on mixed-signal systems which appear strongly nonlinear in the voltage domain but are linear in other variable domains. Common circuits like phase/delay-locked loops and duty-cycle correctors fall into this category, since they are designed to be linear with respect to phases, delays, and duty-cycles of the input and output clocks, respectively. The method uses variable domain translators to change the variables to which the AC perturbation is applied and from which the AC response is measured. By utilizing the efficient periodic AC (PAC) analysis available in commercial RF simulators, the circuit’s linear transfer function in the desired variable domain can be characterized without relying on extensive transient simulations. Furthermore, the variable domain translators enable the circuits to be macromodeled as weakly-nonlinear systems in the chosen domain and then converted to voltage-domain models, instead of being modeled as strongly-nonlinear systems directly

Scalable trajectory methods for on-demand analog macromodel extraction.

ABSTRACT Trajectory methods sample the state trajectory of a circuit as it simulates in the time domain, and build macromodels by reducing and interpolating among the linearizations created at a suitably spaced subset of the time points visited during training simulations. Unfortunately, moving from simple to industrial circuits requires more extensive training, which creates models too large to interpolate efficiently. To make trajectory methods practical, we describe a scalable interpolation architecture, and the first implementation of a complete trajectory "infrastructure" inside a full SPICE engine. The approach supports arbitrarily large training runs, automatically prunes redundant trajectory samples, supports limited hierarchy, enables incremental macromodel updates, and gives 3-10X speedups for larger circuits

Fast Simulation of Analog Circuit Blocks under Nonstationary Operating Conditions

This paper proposes a black-box behavioral modeling framework for analog circuit blocks operating under small-signal conditions around non-stationary operating points. Such variations may be induced either by changes in the loading conditions or by event-driven updates of the operating point for system performance optimization, e.g., to reduce power consumption. An extension of existing data-driven parameterized reduced-order modeling techniques is proposed that considers the time-varying bias components of the port signals as non-stationary parameters. These components are extracted at runtime by a lowpass filter and used to instantaneously update the matrices of the reduced-order state-space model realized as a SPICE netlist. Our main result is a formal proof of quadratic stability of such Linear Parameter Varying (LPV) models, enabled by imposing a specific model structure and representing the transfer function in a basis of positive functions whose elements constitute a partition of unity. The proposed quadratic stability conditions are easily enforced through a finite set of small-size Linear Matrix Inequalities (LMI), used as constraints during model construction. Numerical results on various circuit blocks including voltage regulators confirm that our approach not only ensures the model stability, but also provides speedup in runtime up to 2 orders of magnitude with respect to full transistor-level circuits

A NOVEL AUTOMATED MODEL GENERATION ALGORITHM FOR HIGH LEVEL FAULT MODELING OF ANALOG CIRCUITS

gh level modelling techniques have been used by researchers from few decades to increase fault simulation speed of analog circuits. However, due to manual model generation, the techniques are tedious and time consuming and unable to reduce analog testing time. To overcome manual modelling limitation, researchers adopt algorithmic support and start using automated model generation (AMG) methods to generate models for high level modelling of analog circuits. AMG models successfully perform HLFM but unfortunately fail to increase high level fault simulation (HLFS) speed compared to full SPICE-circuit simulations. The failure is mainly occurred due to the consumption of multiple models and computational overhead of model switching required capturing nonlinear effects

Addressing Computational Complexity of High Speed Distributed Circuits Using Model Order Reduction

Advanced in the fabrication technology of integrated circuits (ICs) over the last couple of years has resulted in an unparalleled expansion of the functionality of microelectronic systems. Today’s ICs feature complex deep-submicron mixed-signal designs and have found numerous applications in industry due to their lower manufacturing costs and higher performance levels. The tendency towards smaller feature sizes and increasing clock rates is placing higher demands on signal integrity design by highlighting previously negligible interconnect effects such as distortion, reflection, ringing, delay, and crosstalk. These effects if not predicted in the early stages of the design cycle can severely degrade circuit performance and reliability. The objective of this thesis is to develop new model order reduction (MOR) techniques to minimize the computational complexity of non-linear circuits and electronic systems that have delay elements. MOR techniques provide a mechanism to generate reduced order models from the detailed description of the original modified nodal analysis (MNA) formulation. The following contributions are made in this thesis: 1. The first project presents a methodology for reduction of Partial Element Equivalent Circuit (PEEC) models. PEEC method is widely used in electromagnetic compatibility and signal integrity problems in both the time and frequency domains. The PEEC model with retardation has been applied to 3-D analysis but often result in large and dense matrices, which are computationally expensive to solve. In this thesis, a new moment matching technique based on Multi-order Arnoldi is described to model PEEC networks with retardation. 2. The second project deals with developing an efficient model order reduction algorithm for simulating large interconnect networks with nonlinear elements. The proposed methodology is based on a multidimensional subspace method and uses constraint equations to link the nonlinear elements and biasing sources to the reduced order model. This approach significantly improves the simulation time of distributed nonlinear systems, since additional ports are not required to link the nonlinear elements to the reduced order model, yielding appreciable savings in the size of the reduced order model and computational time. 3. A parameterized reduction technique for nonlinear systems is presented. The proposed method uses multidimensional subspace and variational analysis to capture the variances of design parameters and approximates the weakly nonlinear functions as a Taylor series. An SVD approach is presented to address the efficiency of reduced order model. The proposed methodology significantly improves the simulation time of weakly nonlinear systems since the size of the reduced system is smaller than the original system and a new reduced model is not required each time a design parameter is changed