ECG noise cancellation using digital filters

A digital filter structure is proposed to maximally remove noise from the ECG signals. This structure is based on cascading a zero-phase bandpass, an adaptive filter, and multi-band-pass filter. It provides an efficient method for removing noise from the ECG signals. This filter structure has low implementation complexity and introduces little noise into a typical ECG. It can be applied to real-time applications particularly automatic cardiac arrhythmia classifiers

Design of an Efficient Retimed CIC Compensation Filter

Unwanted side effects because of spectral aliasing and spectral imaging during signal processing would be the major concern over the sampling rate alteration. Multirate-multistage implementation of digital filter could come about a large computational saving than single rate filter suitable for sample rate conversion. This implementation can further improved through high-level architectural transformation in circuit level. Reallocating registers and relocating flip-flops across logic gates through retiming certainly a prominent sequential transformation technology that optimize hardware circuits to achieve faster clocking speed without affecting the functionality. In this paper, we proposed an efficient compensated cascade Integrator comb (CIC) decimation filter structure that analyze the consequence of filter order variation which has a retimed FIR filter being compensator while using the cutset retiming technique and achieved an improvement in the passband droop by 14% to 39%, in computation time by 38.04%, 25.78%, 12.21%, 6.69% and 4.44% and reduction in path delay by 62.27%, 72%, 86.63%, 91.56% and 94.42% of 3, 6, 8, 12 and 24 order filter respectively than the non-retimed CIC compensation filter

COMPLEX DIGITAL SIGNAL PROCESSING USING QUADRATIC RESIDUE NUMBER SYSTEMS.

This work presents the development of complex digital signal processing algorithms using number theoretic techniques. Residue number principles and techniques are applied to process complex signal information in Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) digital filters. Residue coding of complex samples and arithmetic for processing complex data have been presented using principles of quadratic residues in the Residue Number System (RNS). In this work, we have presented modifications to the Quadratic Residue Number System (QRNS), which we have termed the Modified Quadratic Residue Number System (MQRNS), to process complex integers. New results and theorems have been obtained for the selection of operators to code complex integers into the new MQRNS representation. A novel scheme for residue to binary conversion has been presented for implementation using both the QRNS and MQRNS. Hardware implementations of multiplication intensive complex nonrecursive and recursive digital filters have been presented where the QRNS and MQRNS structures are realized using a bit-slice architectural approach. The computation of Complex Number Theoretic Transforms (CNTTs) and the hardware implementation of a radix-2 NTT butterfly structure, using high density ROM arrays, are presented in both the QRNS and MQRNS systems. As an illustration, the computation of the CNTT developed in this work, is used to compute Cyclic Convolution for complex sequences. These results are verified by computer programs. The recursive FIR filter structure for uniformly spaced frequency samples on the unit circle developed by adapting the Complex Number Theoretic z-transform, has been implemented using the QRNS and MQRNS. In this work, the filter structure is extended for non-uniformly spaced frequency samples and has been termed the generalized number theoretic filter structure. It is shown that for the implementation of this generalized structure, the MQRNS is more efficient than the conventional RNS; the QRNS does not support appropriate fields for the generalized structure.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1985 .K757. Source: Dissertation Abstracts International, Volume: 46-08, Section: B, page: 2757. Thesis (Ph.D.)--University of Windsor (Canada), 1985

Multiplierless CSD techniques for high performance FPGA implementation of digital filters.

I leverage FastCSD to develop a new, high performance iterative multiplierless structure based on a novel real-time CSD recoding, so that more zero partial products are introduced. Up to 66.7% zero partial products occur compared to 50% in the traditional modified Booth's recoding. Also, this structure reduces the non-zero partial products to a minimum. As a result, the number of arithmetic operations in the carry-save structure is reduced. Thus, an overall speed-up, as well as low-power consumption can be achieved. Furthermore, because the proposed structure involves real time CSD recoding and does not require a fixed value for the multiplier input to be known a priori, the proposed multiplier can be applied to implement digital filters with non-fixed filter coefficients, such as adaptive filters.My work is based on a dramatic new technique for converting between 2's complement and CSD number systems, and results in high-performance structures that are particularly effective for implementing adaptive systems in reconfigurable logic.My research focus is on two key ideas for improving DSP performance: (1) Develop new high performance, efficient shift-add techniques ("multiplierless") to implement the multiply-add operations without the need for a traditional multiplier structure. (2) There is a growing trend toward design prototyping and even production in FPGAs as opposed to dedicated DSP processors or ASICs; leverage this trend synergistically with the new multiplierless structures to improve performance.Implementation of digital signal processing (DSP) algorithms in hardware, such as field programmable gate arrays (FPGAs), requires a large number of multipliers. Fast, low area multiply-adds have become critical in modern commercial and military DSP applications. In many contemporary real-time DSP and multimedia applications, system performance is severely impacted by the limitations of currently available speed, energy efficiency, and area requirement of an onboard silicon multiplier.I also introduce a new multi-input Canonical Signed Digit (CSD) multiplier unit, which requires fewer shift/add/subtract operations and reduced CSD number conversion overhead compared to existing techniques. This results in reduced power consumption and area requirements in the hardware implementation of DSP algorithms. Furthermore, because all the products are produced simultaneously, the multiplication speed and thus the throughput are improved. The multi-input multiplier unit is applied to implement digital filters with non-fixed filter coefficients, such as adaptive filters. The implementation cost of these digital filters can be further reduced by limiting the wordlength of the input signal with little or no sacrifice to the filter performance, which is confirmed by my simulation results. The proposed multiplier unit can also be applied to other DSP algorithms, such as digital filter banks or matrix and vector multiplications.Finally, the tradeoff between filter order and coefficient length in the design and implementation of high-performance filters in Field Programmable Gate Arrays (FPGAs) is discussed. Non-minimum order FIR filters are designed for implementation using Canonical Signed Digit (CSD) multiplierless implementation techniques. By increasing the filter order, the length of the coefficients can be decreased without reducing the filter performance. Thus, an overall hardware savings can be achieved.Adaptive system implementations require real-time conversion of coefficients to Canonical Signed Digit (CSD) or similar representations to benefit from multiplierless techniques for implementing filters. Multiplierless approaches are used to reduce the hardware and increase the throughput. This dissertation introduces the first non-iterative hardware algorithm to convert 2's complement numbers to their CSD representations (FastCSD) using a fixed number of shift and logic operations. As a result, the power consumption and area requirements required for hardware implementation of DSP algorithms in which the coefficients are not known a priori can be greatly reduced. Because all CSD digits are produced simultaneously, the conversion speed and thus the throughput are improved when compared to overlap-and-scan techniques such as Booth's recoding

On the Implementation of Efficient Channel Filters for Wideband Receivers by Optimizing Common Subexpression Elimination Methods

No abstract availabl

Efficient Adaptive Filter Algorithms Using Variable Tap-length Scheme

Today the usage of digital signal processors has increased, where adaptive filter algorithms are now routinely employed in mostly all contemporary devices such as mobile phones, camcorders, digital cameras, and medical monitoring equipment, to name few. The filter tap-length, or the number of taps, is a significant structural parameter of adaptive filters that can influences both the complexity and steady-state performance characteristics of the filter. Traditional implementation of adaptive filtering algorithms presume some fixed filter-length and focus on estimating variable filter\u27s tap-weights parameters according to some pre-determined cost function. Although this approach can be adequate in some applications, it is not the case in more complicated ones as it does not answer the question of filter size (tap-length). This problem can be more apparent when the application involves a change in impulse response, making it hard for the adaptive filter algorithm to achieve best potential performance. A cost-effective approach is to come up with variable tap-length filtering scheme that can search for the optimal length while the filter is adapting its coefficients. In direct form structure filtering, commonly known as a transversal adaptive filter, several schemes were used to estimate the optimum tap-length. Among existing algorithms, pseudo fractional tap-length (FT) algorithm, is of particular interest because of its fast convergence rate and small steady-state error. Lattice structured adaptive filters, on the other hand, have attracted attention recently due to a number of desirable properties. The aim of this research is to develop efficient adaptive filter algorithms that fill the gap where optimal filter structures were not proposed by incorporating the concept of pseudo fractional tap-length (FT) in adaptive filtering algorithms. The contribution of this research include the development of variable length adaptive filter scheme and hence optimal filter structure for the following applications: (1) lattice prediction; (2) Least-Mean-Squares (LMS) lattice system identification; (3) Recursive Least-Squares (RLS) lattice system identification; (4) Constant Modulus Algorithm (CMA) blind equalization. To demonstrate the capability of proposed algorithms, simulations examples are implemented in different experimental conditions, where the results showed noticeable improvement in the context of mean square Error (MSE), as well as in the context of convergence rate of the proposed algorithms with their counterparts adaptive filter algorithms. Simulation results have also proven that with affordable extra computational complexity, an optimization for both of the adaptive filter coefficients and the filter tap-length can be attained

Hardware Implementation Of Tunable Heterodyne Band-Pass Filters

Modem wireless and satellite communication systems make use of spreadspectrum modulation concepts such as Frequency-hopping spread-spectrum (FHSS) and Direct sequence spread-spectrum (DSSS). The spread-spectrum modulation method inherently possesses anti-jamming and anti-interception properties due to the fact that the narrowband information signal is spread over a wide range of frequencies, masking the information-bearing signal as noise. Despite these properties, these communication channels can be severely corrupted by high-powered narrowband interference signals generated by local FM or AM transmitters which may cause complications when detecting the information signal at the receiver. Therefore, the communication system is made more efficient with the use of signal processing techniques for narrowband interference attenuation. Control systems is another area where the presence of narrowband interference signal due to mechanical resonance can be responsible for causing distortion in information signal. Any Band-pass, High-pass or a Low-pass filter may be converted into a tunable filter through the use of new Tunable Heterodyne Band-pass Filter concept in which the frequency of the heterodyne signal is adjusted thereby creating the effect of translating the entire transfer function of the fixed filter in frequency. In this thesis, hardware implementation techniques and results of the new Digital Tunable Heterodyne Band-pass filter is proposed that allows a prototype IIR or FIR filter to be shifted through the entire range of digital frequencies with a single parameter, the heterodyning frequency. The unique property of this new tunable filter is the range of tunability it possesses. With this technique, the fixed filter is tuned continuously using the concept of frequency translation. The images created by the heterodyne process are cancelled without the use of image canceling filters, which significantly contribute towards a hardware efficient design. In this thesis, simulation results are observed to illustrate the effects ofhaving the fixed prototype filter as a band-pass, high-pass, low-pass or notch filter. This thesis concentrates on the hardware implementation of the tunable heterodyne filter structure with a band-pass filter as the fixed prototype filter. Thus, simulation and experimental results show that if the fixed filter is a narrowband Bandpass filter, a much hardware efficient implementation can be achieved by using the new Tunable Heterodyne Band-pass filter to extract the narrowband interference from broadband communication or control systems as compared to the standard techniques used. The proposed heterodyne filter is suitable both as a tunable filter or to be implemented with standard algorithms to design adaptive digital filters. The new structure proposed is composed of three main components which can be implemented using Field Programmable Gate Arrays (FPGA) or easily be retargeted for an Application Specific Integrated Circuits (ASIC) standard cell technology or custom designed for Very Large Scale Integration (VLSI) processes. A prototype system is implemented using a single chip Xilinx Virtex Series Field Programmable Gate Arrays (FPGA) and thesimulation results are compared with the hardware data

Design of doubly-complementary IIR digital filters using a single complex allpass filter, with multirate applications

It is shown that a large class of real-coefficient doubly-complementary IIR transfer function pairs can be implemented by means of a single complex allpass filter. For a real input sequence, the real part of the output sequence corresponds to the output of one of the transfer functions G(z) (for example, lowpass), whereas the imaginary part of the output sequence corresponds to its "complementary" filter H(z)(for example, highpass). The resulting implementation is structurally lossless, and hence the implementations of G(z) and H(z) have very low passband sensitivity. Numerical design examples are included, and a typical numerical example shows that the new implementation with 4 bits per multiplier is considerably better than a direct form implementation with 9 bits per multiplier. Multirate filter bank applications (quadrature mirror filtering) are outlined