Low-complexity RLS algorithms using dichotomous coordinate descent iterations

In this paper, we derive low-complexity recursive least squares (RLS) adaptive filtering algorithms. We express the RLS problem in terms of auxiliary normal equations with respect to increments of the filter weights and apply this approach to the exponentially weighted and sliding window cases to derive new RLS techniques. For solving the auxiliary equations, line search methods are used. We first consider conjugate gradient iterations with a complexity of O(N-2) operations per sample; N being the number of the filter weights. To reduce the complexity and make the algorithms more suitable for finite precision implementation, we propose a new dichotomous coordinate descent (DCD) algorithm and apply it to the auxiliary equations. This results in a transversal RLS adaptive filter with complexity as low as 3N multiplications per sample, which is only slightly higher than the complexity of the least mean squares (LMS) algorithm (2N multiplications). Simulations are used to compare the performance of the proposed algorithms against the classical RLS and known advanced adaptive algorithms. Fixed-point FPGA implementation of the proposed DCD-based RLS algorithm is also discussed and results of such implementation are presented

FPGA Implementation of Spectral Subtraction for In-Car Speech Enhancement and Recognition

The use of speech recognition in noisy environments requires the use of speech enhancement algorithms in order to improve recognition performance. Deploying these enhancement techniques requires significant engineering to ensure algorithms are realisable in electronic hardware. This paper describes the design decisions and process to port the popular spectral subtraction algorithm to a Virtex-4 field-programmable gate array (FPGA) device. Resource analysis shows the final design uses only 13% of the total available FPGA resources. Waveforms and spectrograms presented support the validity of the proposed FPGA design

PIC 18F452 implementation of digital filters

This research hopes to explore the computational limits of the PIC18f452 chip by encompassing the designing and implementation of two types of filters for the PIC 18F452 microcontroller. The main purpose of this research is to implement a floating-point least mean square (LMS) error adaptive filter and its secondary goal is a fixed-point implementation of finite impulse response (FIR) filter. FIR filters are specified via a graphical user interface (GUI) and upon demand, optimized C-language code is generated for the popular CCS PIC C-Compiler. In is the intent of this research to learn whether FIR filters can be made computationally viable on the PIC18 chips, can they run stably with reliable and repeatable performance? What is the minimum execution time possible at the processing limits of the chip? And how is filter attenuation affected when taps are scaled down from floating-point to fixed point? The FIR filter code generation software developed during this study allows graphical specification, inspection of response curves. (Abstract shortened by UMI.)

Adaptive Nonlinear RF Cancellation for Improved Isolation in Simultaneous Transmit-Receive Systems

This paper proposes an active radio frequency (RF) cancellation solution to suppress the transmitter (TX) passband leakage signal in radio transceivers supporting simultaneous transmission and reception. The proposed technique is based on creating an opposite-phase baseband equivalent replica of the TX leakage signal in the transceiver digital front-end through adaptive nonlinear filtering of the known transmit data, to facilitate highly accurate cancellation under a nonlinear TX power amplifier (PA). The active RF cancellation is then accomplished by employing an auxiliary transmitter chain, to generate the actual RF cancellation signal, and combining it with the received signal at the receiver (RX) low noise amplifier (LNA) input. A closed-loop parameter learning approach, based on the decorrelation principle, is also developed to efficiently estimate the coefficients of the nonlinear cancellation filter in the presence of a nonlinear TX PA with memory, finite passive isolation, and a nonlinear RX LNA. The performance of the proposed cancellation technique is evaluated through comprehensive RF measurements adopting commercial LTE-Advanced transceiver hardware components. The results show that the proposed technique can provide an additional suppression of up to 54 dB for the TX passband leakage signal at the RX LNA input, even at considerably high transmit power levels and with wide transmission bandwidths. Such novel cancellation solution can therefore substantially improve the TX-RX isolation, hence reducing the requirements on passive isolation and RF component linearity, as well as increasing the efficiency and flexibility of the RF spectrum use in the emerging 5G radio networks.Comment: accepted to IEE

REAL-TIME ADAPTIVE PULSE COMPRESSION ON RECONFIGURABLE, SYSTEM-ON-CHIP (SOC) PLATFORMS

New radar applications need to perform complex algorithms and process a large quantity of data to generate useful information for the users. This situation has motivated the search for better processing solutions that include low-power high-performance processors, efficient algorithms, and high-speed interfaces. In this work, hardware implementation of adaptive pulse compression algorithms for real-time transceiver optimization is presented, and is based on a System-on-Chip architecture for reconfigurable hardware devices. This study also evaluates the performance of dedicated coprocessors as hardware accelerator units to speed up and improve the computation of computing-intensive tasks such matrix multiplication and matrix inversion, which are essential units to solve the covariance matrix. The tradeoffs between latency and hardware utilization are also presented. Moreover, the system architecture takes advantage of the embedded processor, which is interconnected with the logic resources through high-performance buses, to perform floating-point operations, control the processing blocks, and communicate with an external PC through a customized software interface. The overall system functionality is demonstrated and tested for real-time operations using a Ku-band testbed together with a low-cost channel emulator for different types of waveforms

A Digital Predistortion Scheme Exploiting Degrees-of-Freedom for Massive MIMO Systems

The primary source of nonlinear distortion in wireless transmitters is the power amplifier (PA). Conventional digital predistortion (DPD) schemes use high-order polynomials to accurately approximate and compensate for the nonlinearity of the PA. This is not practical for scaling to tens or hundreds of PAs in massive multiple-input multiple-output (MIMO) systems. There is more than one candidate precoding matrix in a massive MIMO system because of the excess degrees-of-freedom (DoFs), and each precoding matrix requires a different DPD polynomial order to compensate for the PA nonlinearity. This paper proposes a low-order DPD method achieved by exploiting massive DoFs of next-generation front ends. We propose a novel indirect learning structure which adapts the channel and PA distortion iteratively by cascading adaptive zero forcing precoding and DPD. Our solution uses a 3rd order polynomial to achieve the same performance as the conventional DPD using an 11th order polynomial for a 100x10 massive MIMO configuration. Experimental results show a 70% reduction in computational complexity, enabling ultra-low latency communications.Comment: IEEE International Conference on Communications 201