A Brand-New, Area - Efficient Architecture for the FFT Algorithm Designed for Implementation of FPGAs

Elliptic curve cryptography, which is more commonly referred to by its acronym ECC, is widely regarded as one of the most effective new forms of cryptography developed in recent times. This is primarily due to the fact that elliptic curve cryptography utilises excellent performance across a wide range of hardware configurations in addition to having shorter key lengths. A High Throughput Multiplier design was described for Elliptic Cryptographic applications that are dependent on concurrent computations. A Proposed (Carry-Select) Division Architecture is explained and proposed throughout the whole of this work. Because of the carry-select architecture that was discussed in this article, the functionality of the divider has been significantly enhanced. The adder carry chain is reduced in length by this design by a factor of two, however this comes at the expense of additional adders and control. When it comes to designs for high throughput FFT, the total number of butterfly units that are implemented is what determines the amount of space that is needed by an FFT processor. In addition to blocks that may either add or subtract numbers, each butterfly unit also features blocks that can multiply numbers. The size of the region that is covered by these dual mathematical blocks is decided by the bit resolution of the models. When the bit resolution is increased, the area will also increase. The standard FFT approach requires that each stage contain  times as many butterfly units as the stage before it. This requirement must be met before moving on to the next stage

6G White Paper on Machine Learning in Wireless Communication Networks

The focus of this white paper is on machine learning (ML) in wireless communications. 6G wireless communication networks will be the backbone of the digital transformation of societies by providing ubiquitous, reliable, and near-instant wireless connectivity for humans and machines. Recent advances in ML research has led enable a wide range of novel technologies such as self-driving vehicles and voice assistants. Such innovation is possible as a result of the availability of advanced ML models, large datasets, and high computational power. On the other hand, the ever-increasing demand for connectivity will require a lot of innovation in 6G wireless networks, and ML tools will play a major role in solving problems in the wireless domain. In this paper, we provide an overview of the vision of how ML will impact the wireless communication systems. We first give an overview of the ML methods that have the highest potential to be used in wireless networks. Then, we discuss the problems that can be solved by using ML in various layers of the network such as the physical layer, medium access layer, and application layer. Zero-touch optimization of wireless networks using ML is another interesting aspect that is discussed in this paper. Finally, at the end of each section, important research questions that the section aims to answer are presented

Secure Communication in wise Homes using IoT

The advancement of the Internet of Things has madeextraordinary progress in recent years in academic as well as industrial fields. There are quite a few wise home systems (WHSs) that have been developed by major companies to achieve home automation. However, the nature of wise homesinescapable raises security and privacy concerns. In this paper, we propose an improved energy-efficient, secure, and privacy-preserving com-munication protocol for the WHSs. In our proposed scheme, data transmissions within the WHS are secured by a symmetric encryption scheme with secret keys being generated by anarchicsystems. Meanwhile, we incorporate message authentication codes to our scheme to guarantee data integrity and authenticity. We also provide detailed security analysis and performance evaluation in comparison with our previous work in terms of computational complexity, memory cost, and communication overhead

Maruchi OS kankyo o shiensuru sofutowea oyobi hadowea kino no teian

制度:新 ; 報告番号:甲3534号 ; 学位の種類:博士(工学) ; 授与年月日:2012/2/25 ; 早大学位記番号:新587

Vector support for multicore processors with major emphasis on configurable multiprocessors

It recently became increasingly difficult to build higher speed uniprocessor chips because of performance degradation and high power consumption. The quadratically increasing circuit complexity forbade the exploration of more instruction-level parallelism (JLP). To continue raising the performance, processor designers then focused on thread-level parallelism (TLP) to realize a new architecture design paradigm. Multicore processor design is the result of this trend. It has proven quite capable in performance increase and provides new opportunities in power management and system scalability. But current multicore processors do not provide powerful vector architecture support which could yield significant speedups for array operations while maintaining arealpower efficiency. This dissertation proposes and presents the realization of an FPGA-based prototype of a multicore architecture with a shared vector unit (MCwSV). FPGA stands for Filed-Programmable Gate Array. The idea is that rather than improving only scalar or TLP performance, some hardware budget could be used to realize a vector unit to greatly speedup applications abundant in data-level parallelism (DLP). To be realistic, limited by the parallelism in the application itself and by the compiler\u27s vectorizing abilities, most of the general-purpose programs can only be partially vectorized. Thus, for efficient resource usage, one vector unit should be shared by several scalar processors. This approach could also keep the overall budget within acceptable limits. We suggest that this type of vector-unit sharing be established in future multicore chips. The design, implementation and evaluation of an MCwSV system with two scalar processors and a shared vector unit are presented for FPGA prototyping. The MicroBlaze processor, which is a commercial IP (Intellectual Property) core from Xilinx, is used as the scalar processor; in the experiments the vector unit is connected to a pair of MicroBlaze processors through standard bus interfaces. The overall system is organized in a decoupled and multi-banked structure. This organization provides substantial system scalability and better vector performance. For a given area budget, benchmarks from several areas show that the MCwSV system can provide significant performance increase as compared to a multicore system without a vector unit. However, a MCwSV system with two MicroBlazes and a shared vector unit is not always an optimized system configuration for various applications with different percentages of vectorization. On the other hand, the MCwSV framework was designed for easy scalability to potentially incorporate various numbers of scalar/vector units and various function units. Also, the flexibility inherent to FPGAs can aid the task of matching target applications. These benefits can be taken into account to create optimized MCwSV systems for various applications. So the work eventually focused on building an architecture design framework incorporating performance and resource management for application-specific MCwSV (AS-MCwSV) systems. For embedded system design, resource usage, power consumption and execution latency are three metrics to be used in design tradeoffs. The product of these metrics is used here to choose the MCwSV system with the smallest value

A study on coarse-grained placement and routing for low-power FPGA architecture

制度:新 ; 報告番号:甲3603号 ; 学位の種類:博士(工学) ; 授与年月日:2012/3/15 ; 早大学位記番号:新595

Low-Power Pıc-Based Sensor Node Devıce Desıgn And Theoretıcal Analysıs Of Energy Consumptıon In Wıreless Sensor Networks

Teknolojinin ilerlemesi, daha enerji verimli ve daha ucuz elektronik bileşenlerinin daha küçük üretilmesini sağlamıştır. Bu nedenle, daha önce mevcut birçok bilgisayar ve elektronik bilim-mühendislik fikirleri uygulanabilir hale gelmiştir. Bunlardan birisi de kablosuz sensör ağları teknolojisidir. Kablosuz algılayıcı ağlar, düşük enerji tüketimi ve gerekli teknik gereksinimlerin gerçekleşmesi ile uygulanabilir hale gelmiştir. Ayrıca, Kablosuz algılayıcı ağlarının tasarımında iletişim algoritmaları, enerji tasarruf protokolleri ve yenilenebilir enerji teknolojileri gibi diğer bilimsel çalışmalar zorunlu hale gelmiştir. Bu tez, mikroelektronik sistemler, kablosuz iletişim ve dijital elektronik teknolojisinin ilerlemesiyle uygulanabilir hale gelmiş sensör ağları teknolojisini kapsamaktadır. Birincisi, algılama görevleri ve potansiyel algılayıcı ağ uygulamaları araştırılmış ve algılayıcı ağlarının tasarımını etkileyen faktörlerin gözden geçirilmesi sağlanmıştır. Ardından sensör ağları için iletişim mimarisi ana hatlarıyla belirtilmiştir. Ayrıca, tek bir düğümün WLAN ile iletişim kurabilmesi için yeni donanım mimarisi tasarlanmış ve düğümlerde yenilenebilir enerji kaynakları kullanılmıştır. Bu tezde WSN, analitik bilim ve uygulamalı bilim açısından incelenmiştir. Düşük enerji tüketimi ve iletişim protokolleri arasındaki ilişki değerlendirilmiş ve bilimsel sonuçlara varılmıştır. Teorik analizler bilimsel uygulamalarla desteklenmiştir. Çalışmalar, düşük enerji ve maksimum verimlilik prensibinin gerçekleştirilmesine dayalı kablosuz sensör ağları üzerinde gerçekleştirilmiştir. Kablosuz sensör ağlari sistemi tasarlandıktan sonra; sensör düğümlerinin enerji tüketimi ve kablosuz ağdaki davranışları test ve analiz edilmiştir. Düşük enerji tüketimi ile sensör düğümleri arasındaki ilişki detaylı olarak değerlendirilmiştir. PIC Tabanlı mikro denetleyiciler sensör düğümlerinin tasarımında kullanılmış ve çok düşük maliyetli tasarım için ultra düşük güçte, nanoWatt teknolojisi ile desteklenen sensör düğümleri tasarlanmıştır. İşleme birimi, bellek birimi ve kablosuz iletişim birimi sensör viii düğümlerine entegre edilmiştir. Tasarlanan sensör düğümünün işletim sistemi PIC C dili ile yazılmıştır ve PIC işletim sistemi nem, sıcaklık, ışığa duyarlılık ve duman sensörü gibi farklı özelliklerin ölçülmesine izin vermiştir. Sensörlerden gelen verilerin merkezi bir konumdan kaydedilmesi ve izlenebilmesi için, C# programlama dili ile bilgisayar yazılımı geliştirilmiştir. Gelişmiş algılayıcı düğümler tarafından alınan kararların uygulanması için yazılım algoritması ve donanım modüllerini içeren karar verme sistemi tasarlanmıştır. Gelişmiş PIC Tabanlı sensör düğümleri, enerji üretimi ve enerji tasarrufu için, güneş enerjisi paneli, şarj edilebilir pil ve süper kapasitör gibi yenilenebilir enerji kaynakları ile benzersiz bir PIC Kontrollü voltaj birimi ile desteklenmiştir. Geliştirilmiş kablosuz sensör ağları sistemi, endüstri uygulamaları, akıllı fabrikalar ve akıllı evler gibi günlük hayat uygulamaları için de kullanılabilecektir. Kablosuz algılayıcı ağlar geniş bir aralıkta kullanılmak üzere tasarlanmıştır. Tezin sonuçları, özellikle yenilenebilir enerji kaynakları ile WSN'nin geliştirilmesine yardımcı olmayı amaçlamaktadır

Low power processor architecture and multicore approach for embedded systems

13301甲第4319号博士（工学）金沢大学博士論文本文Full 以下に掲載：1.IEICE Transactions Vol. E98-C(7) pp.544-549 2015. IEICE. 共著者： S. Otani, H. Kondo. /2.Reuse 許可エビデンス送