A Time-predictable Memory Network-on-Chip

To derive safe bounds on worst-case execution times (WCETs), all components of a computer system need to be time-predictable: the processor pipeline, the caches, the memory controller, and memory arbitration on a multicore processor. This paper presents a solution for time-predictable memory arbitration and access for chip-multiprocessors. The memory network-on-chip is organized as a tree with time-division multiplexing (TDM) of accesses to the shared memory. The TDM based arbitration completely decouples processor cores and allows WCET analysis of the memory accesses on individual cores without considering the tasks on the other cores. Furthermore, we perform local, distributed arbitration according to the global TDM schedule. This solution avoids a central arbiter and scales to a large number of processors

XIRU: Interface de Rede Extensível para Integração de Núcleos a uma Rede-em-Chip

Para a integração dos núcleos de um sistema integrado a uma NoC (Network-on-Chip), é necessário o uso de interfaces de comunicação que realizem a adaptação do protocolo dos núcleos ao da rede e que ofereçam os serviços de comunicação necessários aos núcleos. Este artigo descreve a arquitetura de uma interface de rede extensível para a integração de núcleos à NoC SoCIN (System-on-Chip Interconnection Network). A interface proposta utiliza uma arquitetura estruturada em três camadas que realizam a adaptação do protocolo, o empacotamento/desempacotamento de dados e o envio/recepção de pacotes, entre outros serviços. O artigo descreve a arquitetura da interface de rede e apresenta os resultados de sua validação e síntese em silício

An area-efficient network interface for a TDM-based Network-on-Chip

Network interfaces (NIs) are used in multi-core systems where they connect processors, memories, and other IP-cores to a packet switched Network-on-Chip (NOC). The functionality of a NI is to bridge between the read/write transaction interfaces used by the cores and the packet-streaming interface used by the routers and links in the NOC. The paper addresses the design of a NI for a NOC that uses time division multiplexing (TDM). By keeping the essence of TDM in mind, we have developed a new area-efficient NI micro-architecture. The new design completely eliminates the need for FIFO buffers and credit based flow control - resources which are reported to account for 50–85% of the area in existing NI designs. The paper discusses the design considerations, presents the new NI micro-architecture, and reports area figures for a range of implementations