Modelling and inverting complex-valued Wiener systems

We develop a complex-valued (CV) B-spline neural network approach for efficient identification and inversion of CV Wiener systems. The CV nonlinear static function in the Wiener system is represented using the tensor product of two univariate B-spline neural networks. With the aid of a least squares parameter initialisation, the Gauss-Newton algorithm effectively estimates the model parameters that include the CV linear dynamic model coefficients and B-spline neural network weights. The identification algorithm naturally incorporates the efficient De Boor algorithm with both the B-spline curve and first order derivative recursions. An accurate inverse of the CV Wiener system is then obtained, in which the inverse of the CV nonlinear static function of the Wiener system is calculated efficiently using the Gaussian-Newton algorithm based on the estimated B-spline neural network model, with the aid of the De Boor recursions. The effectiveness of our approach for identification and inversion of CV Wiener systems is demonstrated using the application of digital predistorter design for high power amplifiers with memor

Linear transmitter design for MSAT terminals

One of the factors that will undoubtedly influence the choice of modulation format for mobile satellites, is the availability of cheap, power-efficient, linear amplifiers for mobile terminal equipment operating in the 1.5-1.7 GHz band. Transmitter linearity is not easily achieved at these frequencies, although high power (20W) class A/AB devices are becoming available. However, these components are expensive and require careful design to achieve a modest degree of linearity. In this paper an alternative approach to radio frequency (RF) power amplifier design for mobile satellite (MSAT) terminals using readily-available, power-efficient, and cheap class C devices in a feedback amplifier architecture is presented

Scalable and Energy-Efficient Millimeter Massive MIMO Architectures: Reflect-Array and Transmit-Array Antennas

Hybrid analog-digital architectures are considered as promising candidates for implementing millimeter wave (mmWave) massive multiple-input multiple-output (MIMO) systems since they enable a considerable reduction of the required number of costly radio frequency (RF) chains by moving some of the signal processing operations into the analog domain. However, the analog feed network, comprising RF dividers, combiners, phase shifters, and line connections, of hybrid MIMO architectures is not scalable due to its prohibitively high power consumption for large numbers of transmit antennas. Motivated by this limitation, in this paper, we study novel massive MIMO architectures, namely reflect-array (RA) and transmit-array (TA) antennas. We show that the precoders for RA and TA antennas have to meet different constraints compared to those for conventional MIMO architectures. Taking these constraints into account and exploiting the sparsity of mmWave channels, we design an efficient precoder for RA and TA antennas based on the orthogonal matching pursuit algorithm. Furthermore, in order to fairly compare the performance of RA and TA antennas with conventional fully-digital and hybrid MIMO architectures, we develop a unified power consumption model. Our simulation results show that unlike conventional MIMO architectures, RA and TA antennas are highly energy efficient and fully scalable in terms of the number of transmit antennas.Comment: submitted to IEEE ICC 201

Dynamic selection and estimation of the digital predistorter parameters for power amplifier linearization

© © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a new technique that dynamically estimates and updates the coefficients of a digital predistorter (DPD) for power amplifier (PA) linearization. The proposed technique is dynamic in the sense of estimating, at every iteration of the coefficient's update, only the minimum necessary parameters according to a criterion based on the residual estimation error. At the first step, the original basis functions defining the DPD in the forward path are orthonormalized for DPD adaptation in the feedback path by means of a precalculated principal component analysis (PCA) transformation. The robustness and reliability of the precalculated PCA transformation (i.e., PCA transformation matrix obtained off line and only once) is tested and verified. Then, at the second step, a properly modified partial least squares (PLS) method, named dynamic partial least squares (DPLS), is applied to obtain the minimum and most relevant transformed components required for updating the coefficients of the DPD linearizer. The combination of the PCA transformation with the DPLS extraction of components is equivalent to a canonical correlation analysis (CCA) updating solution, which is optimum in the sense of generating components with maximum correlation (instead of maximum covariance as in the case of the DPLS extraction alone). The proposed dynamic extraction technique is evaluated and compared in terms of computational cost and performance with the commonly used QR decomposition approach for solving the least squares (LS) problem. Experimental results show that the proposed method (i.e., combining PCA with DPLS) drastically reduces the amount of DPD coefficients to be estimated while maintaining the same linearization performance.Peer ReviewedPostprint (author's final draft

Mask Programmable CMOS Transistor Arrays for Wideband RF Integrated Circuits

A mask programmable technology to implement RF and microwave integrated circuits using an array of standard 90-nm CMOS transistors is presented. Using this technology, three wideband amplifiers with more than 15-dB forward transmission gain operating in different frequency bands inside a 4-22-GHz range are implemented. The amplifiers achieve high gain-bandwidth products (79-96 GHz) despite their standard multistage designs. These amplifiers are based on an identical transistor array interconnected with application specific coplanar waveguide (CPW) transmission lines and on-chip capacitors and resistors. CPW lines are implemented using a one-metal-layer post-processing technology over a thick Parylene-N (15 mum ) dielectric layer that enables very low loss lines (~0.6 dB/mm at 20 GHz) and high-performance CMOS amplifiers. The proposed integration approach has the potential for implementing cost-efficient and high-performance RF and microwave circuits with a short turnaround time

Multirate cascaded discrete-time low-pass ΔΣ modulator for GSM/Bluetooth/UMTS

This paper shows that multirate processing in a cascaded discrete-time ΔΣ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time ΔΣ modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded ΔΣ modulator enables the power efficient implementation of multiple communication standards.@The advantages of multirate cascaded ΔΣ modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time ΔΣ modulator. A 2-1 multirate low-pass cascade, with a sampling frequency of 80 MHz in the first stage and 320 MHz in the second stage, meets the requirements for UMTS. The first stage alone is suitable for digitizing Bluetooth and GSM with a sampling frequency of 90 and 50 MHz respectively. This multimode ΔΣ modulator is implemented in a 1.2 V 90 nm CMOS technology with a core area of 0.076 mm2. Measurement results show a dynamic range of 66/77/85 dB for UMTS/ Bluetooth/GSM with a power consumption of 6.8/3.7/3.4 mW. This results in an energy per conversion step of 1.2/0.74/2.86 pJ

Efficient DSP and Circuit Architectures for Massive MIMO: State-of-the-Art and Future Directions

Massive MIMO is a compelling wireless access concept that relies on the use of an excess number of base-station antennas, relative to the number of active terminals. This technology is a main component of 5G New Radio (NR) and addresses all important requirements of future wireless standards: a great capacity increase, the support of many simultaneous users, and improvement in energy efficiency. Massive MIMO requires the simultaneous processing of signals from many antenna chains, and computational operations on large matrices. The complexity of the digital processing has been viewed as a fundamental obstacle to the feasibility of Massive MIMO in the past. Recent advances on system-algorithm-hardware co-design have led to extremely energy-efficient implementations. These exploit opportunities in deeply-scaled silicon technologies and perform partly distributed processing to cope with the bottlenecks encountered in the interconnection of many signals. For example, prototype ASIC implementations have demonstrated zero-forcing precoding in real time at a 55 mW power consumption (20 MHz bandwidth, 128 antennas, multiplexing of 8 terminals). Coarse and even error-prone digital processing in the antenna paths permits a reduction of consumption with a factor of 2 to 5. This article summarizes the fundamental technical contributions to efficient digital signal processing for Massive MIMO. The opportunities and constraints on operating on low-complexity RF and analog hardware chains are clarified. It illustrates how terminals can benefit from improved energy efficiency. The status of technology and real-life prototypes discussed. Open challenges and directions for future research are suggested.Comment: submitted to IEEE transactions on signal processin